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authorCédric Le Goater <clg@kaod.org>2018-06-18 19:05:39 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2018-06-21 21:22:53 +1000
commit77864267c3c82a4938d628b9313bce8fcce6373d (patch)
tree7758bfdc359af572f2d5efe698a524be105dde80 /include
parent7f9fe3f02d9e796e8bcd37628e17127dec515991 (diff)
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ppc/pnv: introduce Pnv8Chip and Pnv9Chip models
It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to define an init and a realize routine which will create the controllers of the target processor. For the moment, the base PnvChip class handles the XSCOM bus and the cores. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
-rw-r--r--include/hw/ppc/pnv.h24
1 files changed, 23 insertions, 1 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 563279f..86d5f54 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -57,12 +57,32 @@ typedef struct PnvChip {
MemoryRegion xscom_mmio;
MemoryRegion xscom;
AddressSpace xscom_as;
+} PnvChip;
+
+#define TYPE_PNV8_CHIP "pnv8-chip"
+#define PNV8_CHIP(obj) OBJECT_CHECK(Pnv8Chip, (obj), TYPE_PNV8_CHIP)
+
+typedef struct Pnv8Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+
+ /*< public >*/
MemoryRegion icp_mmio;
PnvLpcController lpc;
PnvPsi psi;
PnvOCC occ;
-} PnvChip;
+} Pnv8Chip;
+
+#define TYPE_PNV9_CHIP "pnv9-chip"
+#define PNV9_CHIP(obj) OBJECT_CHECK(Pnv9Chip, (obj), TYPE_PNV9_CHIP)
+
+typedef struct Pnv9Chip {
+ /*< private >*/
+ PnvChip parent_obj;
+
+ /*< public >*/
+} Pnv9Chip;
typedef struct PnvChipClass {
/*< private >*/
@@ -75,6 +95,8 @@ typedef struct PnvChipClass {
hwaddr xscom_base;
+ DeviceRealize parent_realize;
+
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);