diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-11-25 07:58:07 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 119eaa9d11cb5245fae0a2cbe4f18dda55744dfb (patch) | |
| tree | aa8e92c412f620692503485aea610be4e25f2a57 /include | |
| parent | 5014c60261cf38b7c210831548c042982218a999 (diff) | |
| download | qemu-119eaa9d11cb5245fae0a2cbe4f18dda55744dfb.zip qemu-119eaa9d11cb5245fae0a2cbe4f18dda55744dfb.tar.gz qemu-119eaa9d11cb5245fae0a2cbe4f18dda55744dfb.tar.bz2 | |
ppc/pnv: Fix TIMA indirect access
When the TIMA of a CPU needs to be accessed from the indirect page,
the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0
register. This thread id is relative to the chip and not to the system.
Introduce a helper routine to look for a CPU of a given PIR and fix
pnv_xive_get_indirect_tctx() to scan only the threads of the local
chip and not the whole machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191125065820.927-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/pnv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 12b0169..a58cfea 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -162,6 +162,8 @@ typedef struct PnvChipClass { #define PNV_CHIP_INDEX(chip) \ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) +PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); + #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") #define PNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) |