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authorAlistair Francis <alistair.francis@wdc.com>2020-10-13 17:17:25 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-10-22 12:00:22 -0700
commit099be0358ee2cfb1cadf80d14297511215885219 (patch)
tree5083e25bb530b6da2fbdbe382476414585ce4dd3 /include
parent1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa (diff)
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hw/riscv: sifive_u: Allow specifying the CPU
Allow the user to specify the main application CPU for the sifive_u machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
Diffstat (limited to 'include')
-rw-r--r--include/hw/riscv/sifive_u.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 22e7e6e..a9f7b4a 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -48,6 +48,7 @@ typedef struct SiFiveUSoCState {
CadenceGEMState gem;
uint32_t serial;
+ char *cpu_type;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")