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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2022-03-05 15:09:56 +0000 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2022-03-09 09:28:28 +0000 |
| commit | b793b4ef8c862891c716cd163aaa7e4af0d697da (patch) | |
| tree | 1e67cac8ca64381fe32c6146edf09756cfa0f4ff /include | |
| parent | 677a4725b1c49b139b00d8eaa932676ed8620931 (diff) | |
| download | qemu-b793b4ef8c862891c716cd163aaa7e4af0d697da.zip qemu-b793b4ef8c862891c716cd163aaa7e4af0d697da.tar.gz qemu-b793b4ef8c862891c716cd163aaa7e4af0d697da.tar.bz2 | |
mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs
The mos6522 datasheet describes how the control lines IRQs are edge-triggered
according to the configuration in the PCR register. Implement the logic according
to the datasheet so that the interrupt bits in IFR are latched when the edge is
detected, and cleared when reading portA/portB or writing to IFR as necessary.
To maintain bisectibility this change also updates the SCSI, SCSI data, Nubus
and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered as
confirmed by the PCR programming in all of Linux, NetBSD and MacOS.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220305150957.5053-12-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/misc/mos6522.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index babea99..0bc22a8 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -65,6 +65,21 @@ #define T1MODE 0xc0 /* Timer 1 mode */ #define T1MODE_CONT 0x40 /* continuous interrupts */ +/* Bits in PCR */ +#define CB2_CTRL_MASK 0xe0 +#define CB2_CTRL_SHIFT 5 +#define CB1_CTRL_MASK 0x10 +#define CB1_CTRL_SHIFT 4 +#define CA2_CTRL_MASK 0x0e +#define CA2_CTRL_SHIFT 1 +#define CA1_CTRL_MASK 0x1 +#define CA1_CTRL_SHIFT 0 + +#define C2_POS 0x2 +#define C2_IND 0x1 + +#define C1_POS 0x1 + /* VIA registers */ #define VIA_REG_B 0x00 #define VIA_REG_A 0x01 |