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authorBernhard Beschow <shentey@gmail.com>2023-02-13 18:30:30 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-02-27 22:29:01 +0100
commite3e3a8ad1216faccd737f6bc06919deb366b0be3 (patch)
tree9437b5e3b1469442e0df33f619baeb2ba52afb75 /include
parentfb1856cb9b7cd81f45e1ee6ce079a4eea59314aa (diff)
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hw/i386/ich9: Remove redundant GSI_NUM_PINS
Most code uses IOAPIC_NUM_PINS. The only place where GSI_NUM_PINS defines the size of an array is ICH9LPCState::gsi which needs to match IOAPIC_NUM_PINS. Remove GSI_NUM_PINS for consistency. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230213173033.98762-10-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/i386/ich9.h2
-rw-r--r--include/hw/i386/x86.h1
2 files changed, 1 insertions, 2 deletions
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 433c894..d29090a 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -63,7 +63,7 @@ struct ICH9LPCState {
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
- qemu_irq gsi[GSI_NUM_PINS];
+ qemu_irq gsi[IOAPIC_NUM_PINS];
};
#define ICH9_MASK(bit, ms_bit, ls_bit) \
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 5d3047a..a09388b 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -131,7 +131,6 @@ bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
/* Global System Interrupts */
-#define GSI_NUM_PINS IOAPIC_NUM_PINS
#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
typedef struct GSIState {