diff options
author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:10 -0700 |
---|---|---|
committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:48 -0700 |
commit | af14c840418bee1b22e5b1bc403dcc8c69492517 (patch) | |
tree | 432e45bec6780943fc6095493ba1d829a6bde658 /include | |
parent | e1724d09a6dc090063cad9d88d9994b9f55f5716 (diff) | |
download | qemu-af14c840418bee1b22e5b1bc403dcc8c69492517.zip qemu-af14c840418bee1b22e5b1bc403dcc8c69492517.tar.gz qemu-af14c840418bee1b22e5b1bc403dcc8c69492517.tar.bz2 |
riscv: sifive_u: Add PRCI block to the SoC
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/riscv/sifive_u.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2441814..bb46745 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -22,6 +22,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" +#include "hw/riscv/sifive_u_prci.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -37,6 +38,7 @@ typedef struct SiFiveUSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + SiFiveUPRCIState prci; CadenceGEMState gem; } SiFiveUSoCState; @@ -55,6 +57,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, |