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author | Michael Clark <mjc@sifive.com> | 2018-03-03 01:31:13 +1300 |
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committer | Michael Clark <mjc@sifive.com> | 2018-03-07 08:30:28 +1300 |
commit | 5b4beba1246ff163415bde41cd76935012b16823 (patch) | |
tree | ac3596e00957f860fefdfdf2503aff64ef229f74 /include | |
parent | 1e24429e40df81270012538851c75e30c53eec21 (diff) | |
download | qemu-5b4beba1246ff163415bde41cd76935012b16823.zip qemu-5b4beba1246ff163415bde41cd76935012b16823.tar.gz qemu-5b4beba1246ff163415bde41cd76935012b16823.tar.bz2 |
RISC-V Spike Machines
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:
- 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/riscv/spike.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h new file mode 100644 index 0000000..cb55a14 --- /dev/null +++ b/include/hw/riscv/spike.h @@ -0,0 +1,53 @@ +/* + * Spike machine interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SPIKE_H +#define HW_SPIKE_H + +#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1" +#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10" + +#define SPIKE(obj) \ + OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + RISCVHartArrayState soc; + void *fdt; + int fdt_size; +} SpikeState; + + +enum { + SPIKE_MROM, + SPIKE_CLINT, + SPIKE_DRAM +}; + +#if defined(TARGET_RISCV32) +#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 +#elif defined(TARGET_RISCV64) +#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 +#endif + +#endif |