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authorPeter Maydell <peter.maydell@linaro.org>2018-10-30 10:45:49 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-10-30 10:45:49 +0000
commit0bbba1665ca2e7f1c80d4797077fe57bad58898e (patch)
treeb2b1d6164243d1e7209e0e0315b1f13b39581cfd /include
parent09ffed7eed62c75b9953555378a4edd79ca1427c (diff)
parent64ea3d676d9447ecdb987deab5a1542ea088bd31 (diff)
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging
MIPS queue for October 2018, part 4 # gpg: Signature made Mon 29 Oct 2018 15:11:32 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-october-2018-part-4: (27 commits) linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations linux-user: Determine the desired FPU mode from MIPS.abiflags linux-user: Read and set FP ABI value from MIPS abiflags linux-user: Extract MIPS abiflags from ELF file linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields elf: Define MIPS_ABI_FP_UNKNOWN macro target/mips: Amend MXU ASE overview note target/mips: Move MXU_EN check one level higher target/mips: Add emulation of MXU instructions S32LDD and S32LDDR target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU target/mips: Add emulation of MXU instruction D16MAC target/mips: Add emulation of MXU instruction D16MUL target/mips: Add emulation of MXU instruction S8LDD target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch target/mips: Add emulation of MXU instructions S32I2M and S32M2I target/mips: Add emulation of non-MXU MULL within MXU decoding engine target/mips: Add bit encoding for MXU operand getting pattern 'optn3' target/mips: Add bit encoding for MXU operand getting pattern 'optn2' target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/elf.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/elf.h b/include/elf.h
index 5f45f9b..c151164 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -87,6 +87,8 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
+#define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */
+
#define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */
#define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
#define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */