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| author | Greg Kurz <groug@kaod.org> | 2019-12-13 13:00:13 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:59:11 +1100 |
| commit | c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3 (patch) | |
| tree | 3fbf96685d27fcf41f90c33d1700006fce941070 /include | |
| parent | 85913070a6c9fcbe1ac6a043f3278b2982702143 (diff) | |
| download | qemu-c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3.zip qemu-c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3.tar.gz qemu-c4b2c40c0eea3bc8ad286a6a1a62209c4bc332e3.tar.bz2 | |
ppc/pnv: Introduce PnvChipClass::xscom_core_base() method
The pnv_chip_core_realize() function configures the XSCOM MMIO subregion
for each core of a single chip. The base address of the subregion depends
on the CPU type. Its computation is currently open-code using the
pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce
a method for this in the base chip class and implement it in child classes.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/ppc/pnv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7d24027..17ca9a1 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -137,6 +137,7 @@ typedef struct PnvChipClass { ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); } PnvChipClass; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP |