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authorCédric Le Goater <clg@kaod.org>2022-03-02 06:51:39 +0100
committerCédric Le Goater <clg@kaod.org>2022-03-02 06:51:39 +0100
commit95d729e2bc5b46d40e71971043e03d9cc9503e9a (patch)
treee09e1553035ef69f73e5535d235dc34ba29e3e5a /include
parent707ea7ab4d55e0d907f72280eb2e4d376efeddf7 (diff)
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ppc/pnv: add XIVE Gen2 TIMA support
Only the CAM line updates done by the hypervisor are specific to POWER10. Instead of duplicating the TM ops table, we handle these commands locally under the PowerNV XIVE2 model. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/ppc/xive2.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index eb255b6..c8c4505 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -87,5 +87,13 @@ typedef struct Xive2EndSource {
Xive2Router *xrtr;
} Xive2EndSource;
+/*
+ * XIVE2 Thread Interrupt Management Area (POWER10)
+ */
+
+void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size);
+uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size);
#endif /* PPC_XIVE2_H */