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| author | Peter Maydell <peter.maydell@linaro.org> | 2023-01-07 14:25:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-07 14:25:38 +0000 |
| commit | 0ab12aa32462817f0a53fa6f6ce4baf664ef1713 (patch) | |
| tree | dbf26031a50e07eac12bf31fc0d9470b2abb3e39 /include | |
| parent | 052e6534c49ebef8901824b77abc39271f0d852e (diff) | |
| parent | f4d10ce8aa545266a0b6df223a7f8ea2afca18b2 (diff) | |
| download | qemu-0ab12aa32462817f0a53fa6f6ce4baf664ef1713.zip qemu-0ab12aa32462817f0a53fa6f6ce4baf664ef1713.tar.gz qemu-0ab12aa32462817f0a53fa6f6ce4baf664ef1713.tar.bz2 | |
Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into staging
pull-loongarch-20230106
# gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu:
hw/intc/loongarch_pch: Change default irq number of pch irq controller
hw/intc/loongarch_pch_pic: add irq number property
hw/intc/loongarch_pch_msi: add irq number property
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/loongarch_pch_msi.h | 9 | ||||
| -rw-r--r-- | include/hw/intc/loongarch_pch_pic.h | 6 | ||||
| -rw-r--r-- | include/hw/pci-host/ls7a.h | 2 |
3 files changed, 8 insertions, 9 deletions
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h index 6d67560..832e69f 100644 --- a/include/hw/intc/loongarch_pch_msi.h +++ b/include/hw/intc/loongarch_pch_msi.h @@ -8,15 +8,16 @@ #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) -/* Msi irq start start from 64 to 255 */ -#define PCH_MSI_IRQ_START 64 +/* MSI irq start from 32 to 255 */ +#define PCH_MSI_IRQ_START 32 #define PCH_MSI_IRQ_END 255 -#define PCH_MSI_IRQ_NUM 192 +#define PCH_MSI_IRQ_NUM 224 struct LoongArchPCHMSI { SysBusDevice parent_obj; - qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM]; + qemu_irq *pch_msi_irq; MemoryRegion msi_mmio; /* irq base passed to upper extioi intc */ unsigned int irq_base; + unsigned int irq_num; }; diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h index 2d4aa9e..258e3b3 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -9,11 +9,8 @@ #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) -#define PCH_PIC_IRQ_START 0 -#define PCH_PIC_IRQ_END 63 -#define PCH_PIC_IRQ_NUM 64 #define PCH_PIC_INT_ID_VAL 0x7000000UL -#define PCH_PIC_INT_ID_NUM 0x3f0001UL +#define PCH_PIC_INT_ID_VER 0x1UL #define PCH_PIC_INT_ID_LO 0x00 #define PCH_PIC_INT_ID_HI 0x04 @@ -66,4 +63,5 @@ struct LoongArchPCHPIC { MemoryRegion iomem32_low; MemoryRegion iomem32_high; MemoryRegion iomem8; + unsigned int irq_num; }; diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index df7fa55..8061c4b 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -32,9 +32,9 @@ * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs * used for pci device. */ +#define VIRT_PCH_PIC_IRQ_NUM 32 #define PCH_PIC_IRQ_OFFSET 64 #define VIRT_DEVICE_IRQS 16 -#define VIRT_PCI_IRQS 48 #define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) #define VIRT_UART_BASE 0x1fe001e0 #define VIRT_UART_SIZE 0X100 |