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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-04-17 13:22:43 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-01-13 08:39:08 -1000 |
| commit | c58f4c97b2ad9247c5ee85d625a934370862fba1 (patch) | |
| tree | 987dd44a46017e1cc45dcb64fbcc6d07e727c47d /include/tcg | |
| parent | 1bd1af98d7b166ced72e2fb8126b484c86d5357b (diff) | |
| download | qemu-c58f4c97b2ad9247c5ee85d625a934370862fba1.zip qemu-c58f4c97b2ad9247c5ee85d625a934370862fba1.tar.gz qemu-c58f4c97b2ad9247c5ee85d625a934370862fba1.tar.bz2 | |
tcg: Remove movi and dupi opcodes
These are now completely covered by mov from a
TYPE_CONST temporary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/tcg')
| -rw-r--r-- | include/tcg/tcg-opc.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 4371163..900984c 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -45,7 +45,6 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) -DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) /* load/store */ @@ -111,7 +110,6 @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) -DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) /* load/store */ @@ -221,7 +219,6 @@ DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) -DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) DEF(dup_vec, 1, 1, 0, IMPLVEC) DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) |