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author | Peter Maydell <peter.maydell@linaro.org> | 2020-07-23 19:00:42 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-07-23 19:00:42 +0100 |
commit | 09e0cd773723219d21655587954da2769f64ba01 (patch) | |
tree | 31311a3ce81b39ce56a7bd9cf474fb3d52d96d6a /include/qemu/uri.h | |
parent | 8ffa52c20d5693d454f65f2024a1494edfea65d4 (diff) | |
parent | 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d (diff) | |
download | qemu-09e0cd773723219d21655587954da2769f64ba01.zip qemu-09e0cd773723219d21655587954da2769f64ba01.tar.gz qemu-09e0cd773723219d21655587954da2769f64ba01.tar.bz2 |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200722-1' into staging
This PR contains a few RISC-V fixes.
The main fix is the correction of the goldfish RTC time. On top of that
some small fixes to the recently added vector extensions have been added
(including an assert that fixed a coverity report). There is a change in
the SiFive E debug memory size to match hardware. Finally there is a fix
for PMP accesses.
# gpg: Signature made Wed 22 Jul 2020 17:43:59 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200722-1:
target/riscv: Fix the range of pmpcfg of CSR funcion table
hw/riscv: sifive_e: Correct debug block size
target/riscv: fix vector index load/store constraints
target/riscv: Quiet Coverity complains about vamo*
goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/qemu/uri.h')
0 files changed, 0 insertions, 0 deletions