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| author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
| commit | 34b0696be443e123d2d5225613c4604c66eb7a64 (patch) | |
| tree | 07c0045669a0bc8e25f0c6ef3828bd799fea7bf3 /include/hw | |
| parent | c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664 (diff) | |
| download | qemu-34b0696be443e123d2d5225613c4604c66eb7a64.zip qemu-34b0696be443e123d2d5225613c4604c66eb7a64.tar.gz qemu-34b0696be443e123d2d5225613c4604c66eb7a64.tar.bz2 | |
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
When the Address-Based Interrupt Trigger mode is activated, the PHB
maps the interrupt source number into the interrupt command address.
The PHB directly triggers the IC ESB page of the interrupt number and
not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/pci-host/pnv_phb4_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index 64f326b..4a0d3b2 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -220,12 +220,14 @@ #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63) #define PHB_ETU_ERR_SUMMARY 0x2c8 #define PHB_INT_NOTIFY_ADDR 0x300 +#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */ #define PHB_INT_NOTIFY_INDEX 0x308 /* Fundamental register set B */ #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */ +#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) |