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authorJiaxun Yang <jiaxun.yang@flygoat.com>2023-05-21 11:23:04 +0100
committerSong Gao <gaosong@loongson.cn>2023-06-05 11:08:55 +0800
commit8555ddc671203969b0e6eb651e538d02a9a79b3a (patch)
tree6f76e13a63ebba8c2164493e2fcddd171b85a362 /include/hw
parent848a6caa88b9f082c89c9b41afa975761262981d (diff)
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hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
As per "Loongson 3A5000/3B5000 Processor Reference Manual", Loongson 3A5000's IPI implementation have 4 mailboxes per core. However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device"), the number of IPI mailboxes was reduced to one, which mismatches actual hardware. It won't affect LoongArch based system as LoongArch boot code only uses the first mailbox, however MIPS based Loongson boot code uses all 4 mailboxes. Fixes Coverity CID: 1512452, 1512453 Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com> Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/intc/loongarch_ipi.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index 664e050..6c61947 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -28,6 +28,8 @@
#define MAIL_SEND_OFFSET 0
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
+#define IPI_MBX_NUM 4
+
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
@@ -37,7 +39,7 @@ typedef struct IPICore {
uint32_t set;
uint32_t clear;
/* 64bit buf divide into 2 32bit buf */
- uint32_t buf[2];
+ uint32_t buf[IPI_MBX_NUM * 2];
qemu_irq irq;
} IPICore;