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| author | Cédric Le Goater <clg@kaod.org> | 2019-09-04 09:05:03 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-13 16:05:01 +0100 |
| commit | 5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c (patch) | |
| tree | d5eedd02673f3b18f37f8247b2dcd262adbff7b8 /include/hw | |
| parent | 0d72c717029f59fa0531fee419734ad7f14b1331 (diff) | |
| download | qemu-5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c.zip qemu-5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c.tar.gz qemu-5258c2a69ce6cea0b9ab90f1c83223c0daa8d72c.tar.bz2 | |
aspeed/smc: Inject errors in DMA checksum
Emulate read errors in the DMA Checksum Register for high frequencies
and optimistic settings of the Read Timing Compensation Register. This
will help in tuning the SPI timing calibration algorithm. Errors are
only injected when the property "inject_failure" is set to true as
suggested by Philippe.
The values below are those to expect from the first flash device of
the FMC controller of a palmetto-bmc machine.
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190904070506.1052-8-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/ssi/aspeed_smc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 32ce691..5176ff6 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -88,6 +88,7 @@ typedef struct AspeedSMCState { uint32_t num_cs; qemu_irq *cs_lines; + bool inject_failure; SSIBus *spi; |