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author | Frank Chang <frank.chang@sifive.com> | 2021-02-23 14:59:32 +0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-22 21:54:40 -0400 |
commit | 5e437d3ccdccfd85f6e69ca60f921be2dab62c3c (patch) | |
tree | 443640a16e3517dfffd84c19dd49fff02ee46979 /include/hw | |
parent | c95bd5ff1660883d15ad6e0005e4c8571604f51a (diff) | |
download | qemu-5e437d3ccdccfd85f6e69ca60f921be2dab62c3c.zip qemu-5e437d3ccdccfd85f6e69ca60f921be2dab62c3c.tar.gz qemu-5e437d3ccdccfd85f6e69ca60f921be2dab62c3c.tar.bz2 |
target/riscv: fix vs() to return proper error code
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.
If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
0 files changed, 0 insertions, 0 deletions