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authorCédric Le Goater <clg@kaod.org>2019-09-25 16:32:47 +0200
committerPeter Maydell <peter.maydell@linaro.org>2019-10-15 18:09:05 +0100
commit289251b033979234ed735a7b996a187880ed090e (patch)
tree6abd4d0a0e1c6530e934bdba140c7ddefde17c79 /include/hw
parentd300db02774b2225cd8a527ee6212e093e94fdce (diff)
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aspeed: add support for the Aspeed MII controller of the AST2600
The AST2600 SoC has an extra controller to set the PHY registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-23-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/arm/aspeed_soc.h5
-rw-r--r--include/hw/net/ftgmac100.h17
2 files changed, 22 insertions, 0 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 088a5d1..43478f6 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -52,6 +52,7 @@ typedef struct AspeedSoCState {
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
+ AspeedMiiState mii[ASPEED_MACS_NUM];
AspeedGPIOState gpio;
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
@@ -117,6 +118,10 @@ enum {
ASPEED_ETH2,
ASPEED_ETH3,
ASPEED_ETH4,
+ ASPEED_MII1,
+ ASPEED_MII2,
+ ASPEED_MII3,
+ ASPEED_MII4,
ASPEED_SDRAM,
ASPEED_XDMA,
};
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
index 94cfe05..ab37e7b 100644
--- a/include/hw/net/ftgmac100.h
+++ b/include/hw/net/ftgmac100.h
@@ -66,4 +66,21 @@ typedef struct FTGMAC100State {
uint32_t rxdes0_edorr;
} FTGMAC100State;
+#define TYPE_ASPEED_MII "aspeed-mmi"
+#define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII)
+
+/*
+ * AST2600 MII controller
+ */
+typedef struct AspeedMiiState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ FTGMAC100State *nic;
+
+ MemoryRegion iomem;
+ uint32_t phycr;
+ uint32_t phydata;
+} AspeedMiiState;
+
#endif