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author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-12 10:33:54 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:20 +0100 |
commit | f3eb7557284db7d9eba8843c5705b4dc90dc6fd3 (patch) | |
tree | 7d4c6b64e78be0fe78c1012f4876794c237a1cb6 /include/hw/timer | |
parent | 0d883c540462bed9b6fa64594290edfd27cb0fc0 (diff) | |
download | qemu-f3eb7557284db7d9eba8843c5705b4dc90dc6fd3.zip qemu-f3eb7557284db7d9eba8843c5705b4dc90dc6fd3.tar.gz qemu-f3eb7557284db7d9eba8843c5705b4dc90dc6fd3.tar.bz2 |
hw/arm/stellaris: Split stellaris-gptm into its own file
The implementation of the Stellaris general purpose timer module
device stellaris-gptm is currently in the same source file as the
board model. Split it out into its own source file in hw/timer.
Apart from the new file comment headers and the Kconfig and
meson.build changes, this is just code movement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/timer')
-rw-r--r-- | include/hw/timer/stellaris-gptm.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris-gptm.h new file mode 100644 index 0000000..b8fa43c --- /dev/null +++ b/include/hw/timer/stellaris-gptm.h @@ -0,0 +1,48 @@ +/* + * Luminary Micro Stellaris General Purpose Timer Module + * + * Copyright (c) 2006 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#ifndef HW_TIMER_STELLARIS_GPTM_H +#define HW_TIMER_STELLARIS_GPTM_H + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_STELLARIS_GPTM "stellaris-gptm" +OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM) + +/* + * QEMU interface: + * + sysbus MMIO region 0: register bank + * + sysbus IRQ 0: timer interrupt + * + unnamed GPIO output 0: trigger output for the ADC + */ +struct gptm_state { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t config; + uint32_t mode[2]; + uint32_t control; + uint32_t state; + uint32_t mask; + uint32_t load[2]; + uint32_t match[2]; + uint32_t prescale[2]; + uint32_t match_prescale[2]; + uint32_t rtc; + int64_t tick[2]; + struct gptm_state *opaque[2]; + QEMUTimer *timer[2]; + /* The timers have an alternate output used to trigger the ADC. */ + qemu_irq trigger; + qemu_irq irq; +}; + +#endif |