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authorSai Pavan Boddu <saipava@xilinx.com>2018-06-26 17:50:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-06-26 17:50:39 +0100
commit21d887cde954ca683f37d9c7d20371cdf26686be (patch)
treee60fb0842c9998a80a2a800915f2b479bc443a2d /include/hw/ssi
parent1f7161d2c83a4ebba296ffece26f992be5754471 (diff)
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xilinx_spips: Make dma transactions as per dma_burst_size
Qspi dma has a burst length of 64 bytes, So limit the transactions w.r.t dma-burst-size property. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1529660880-30376-1-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/ssi')
-rw-r--r--include/hw/ssi/xilinx_spips.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index d398a4e..a0a0ae7 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -37,6 +37,8 @@ typedef struct XilinxSPIPS XilinxSPIPS;
/* Bite off 4k chunks at a time */
#define LQSPI_CACHE_SIZE 1024
+#define QSPI_DMA_MAX_BURST_SIZE 2048
+
typedef enum {
READ = 0x3, READ_4 = 0x13,
FAST_READ = 0xb, FAST_READ_4 = 0x0c,
@@ -95,7 +97,6 @@ typedef struct {
XilinxQSPIPS parent_obj;
StreamSlave *dma;
- uint8_t dma_buf[4];
int gqspi_irqline;
uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
@@ -113,6 +114,8 @@ typedef struct {
uint8_t rx_fifo_g_align;
uint8_t tx_fifo_g_align;
bool man_start_com_g;
+ uint32_t dma_burst_size;
+ uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
} XlnxZynqMPQSPIPS;
typedef struct XilinxSPIPSClass {