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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-02-11 19:57:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-02-11 19:57:50 +0000 |
| commit | eac92d316351b855ba79eb374dd21cc367f1f9c1 (patch) | |
| tree | 3dd45330cd46e965e5ac5dfff8379a55df7d497f /include/hw/ssi/pl022.h | |
| parent | c973f06521b07af0f82893b75a1d55562fffb4b5 (diff) | |
| parent | d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621 (diff) | |
| download | qemu-eac92d316351b855ba79eb374dd21cc367f1f9c1.zip qemu-eac92d316351b855ba79eb374dd21cc367f1f9c1.tar.gz qemu-eac92d316351b855ba79eb374dd21cc367f1f9c1.tar.bz2 | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging
target-arm queue:
* Correctly initialize MDCR_EL2.HPMN
* versal: Use nr_apu_cpus in favor of hard coding 2
* accel/tcg: Add URL of clang bug to comment about our workaround
* Add support for FEAT_DIT, Data Independent Timing
* Remove GPIO from unimplemented NPCM7XX
* Fix SCR RES1 handling
* Don't migrate CPUARMState.features
# gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210211-1:
target/arm: Correctly initialize MDCR_EL2.HPMN
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
accel/tcg: Add URL of clang bug to comment about our workaround
arm: Update infocenter.arm.com URLs
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
target/arm: Add support for FEAT_DIT, Data Independent Timing
hw/arm: Remove GPIO from unimplemented NPCM7XX
target/arm: Fix SCR RES1 handling
target/arm: Don't migrate CPUARMState.features
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/ssi/pl022.h')
| -rw-r--r-- | include/hw/ssi/pl022.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/hw/ssi/pl022.h b/include/hw/ssi/pl022.h index 545b526..25d58db 100644 --- a/include/hw/ssi/pl022.h +++ b/include/hw/ssi/pl022.h @@ -9,9 +9,10 @@ * (at your option) any later version. */ -/* This is a model of the Arm PrimeCell PL022 synchronous serial port. +/* + * This is a model of the Arm PrimeCell PL022 synchronous serial port. * The PL022 TRM is: - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/DDI0194H_ssp_pl022_trm.pdf + * https://developer.arm.com/documentation/ddi0194/latest * * QEMU interface: * + sysbus IRQ: SSPINTR combined interrupt line |