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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:06 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:47 -0700 |
| commit | ecdfe393b69985eb90ac4921287439dc47ed35b4 (patch) | |
| tree | 18e3169109e7b7dde7bea572a48d9335bf9949f9 /include/hw/riscv | |
| parent | f3d47d580402d11b73108de807031124c135e370 (diff) | |
| download | qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.zip qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.tar.gz qemu-ecdfe393b69985eb90ac4921287439dc47ed35b4.tar.bz2 | |
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 6d22741..6b2b5b6 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -32,7 +32,10 @@ typedef struct SiFiveUSoCState { SysBusDevice parent_obj; /*< public >*/ - RISCVHartArrayState cpus; + CPUClusterState e_cluster; + CPUClusterState u_cluster; + RISCVHartArrayState e_cpus; + RISCVHartArrayState u_cpus; DeviceState *plic; CadenceGEMState gem; } SiFiveUSoCState; @@ -70,6 +73,7 @@ enum { }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 +#define SIFIVE_U_COMPUTE_CPU_COUNT 4 #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 |