diff options
| author | Markus Armbruster <armbru@redhat.com> | 2022-12-22 13:08:11 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-01-08 01:54:22 -0500 |
| commit | 7a5951f651ad5f158631a826070b24631e733763 (patch) | |
| tree | b114cc7b294fb3a8fc754a040f7a88af2aceeac1 /include/hw/riscv | |
| parent | f139b83717092b4080b85d6edde699d89e41a04c (diff) | |
| download | qemu-7a5951f651ad5f158631a826070b24631e733763.zip qemu-7a5951f651ad5f158631a826070b24631e733763.tar.gz qemu-7a5951f651ad5f158631a826070b24631e733763.tar.bz2 | |
include: Include headers where needed
A number of headers neglect to include everything they need. They
compile only if the headers they need are already included from
elsewhere. Fix that.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221222120813.727830-3-armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/boot_opensbi.h | 2 | ||||
| -rw-r--r-- | include/hw/riscv/microchip_pfsoc.h | 3 | ||||
| -rw-r--r-- | include/hw/riscv/numa.h | 1 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 | ||||
| -rw-r--r-- | include/hw/riscv/spike.h | 2 | ||||
| -rw-r--r-- | include/hw/riscv/virt.h | 2 |
6 files changed, 10 insertions, 2 deletions
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h index c19cad4..1b74966 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -8,6 +8,8 @@ #ifndef RISCV_BOOT_OPENSBI_H #define RISCV_BOOT_OPENSBI_H +#include "exec/cpu-defs.h" + /** Expected value of info magic ('OSBI' ascii string in hex) */ #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index e65ffeb..daef086 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -22,13 +22,16 @@ #ifndef HW_MICROCHIP_PFSOC_H #define HW_MICROCHIP_PFSOC_H +#include "hw/boards.h" #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/cpu/cluster.h" #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/misc/mchp_pfsoc_sysreg.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" +#include "hw/riscv/riscv_hart.h" typedef struct MicrochipPFSoCState { /*< private >*/ diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index fcce942..1a9cce3 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -19,6 +19,7 @@ #ifndef RISCV_NUMA_H #define RISCV_NUMA_H +#include "hw/boards.h" #include "hw/sysbus.h" #include "sysemu/numa.h" diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e680d61..a67328f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,8 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H +#include "hw/boards.h" +#include "hw/cpu/cluster.h" #include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73d6923..73bf2a9 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,9 +19,9 @@ #ifndef HW_RISCV_SPIKE_H #define HW_RISCV_SPIKE_H +#include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" -#include "qom/object.h" #define SPIKE_CPUS_MAX 8 #define SPIKE_SOCKETS_MAX 8 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3407c9e..b3d2613 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,10 @@ #ifndef HW_RISCV_VIRT_H #define HW_RISCV_VIRT_H +#include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" #include "hw/block/flash.h" -#include "qom/object.h" #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) |