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| author | Michael Clark <mjc@sifive.com> | 2018-03-05 09:27:28 +1300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2018-09-04 13:19:23 -0700 |
| commit | c3b03e5800a7151d3c746f40efceabdfdae08f85 (patch) | |
| tree | 0f9711fffef25b426df4b0b2398b393f5571b68d /include/hw/riscv/sifive_plic.h | |
| parent | 718a941e19005492015ae7aa5db04d853b5af877 (diff) | |
| download | qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.zip qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.tar.gz qemu-c3b03e5800a7151d3c746f40efceabdfdae08f85.tar.bz2 | |
RISC-V: Improve page table walker spec compliance
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/sifive_plic.h')
0 files changed, 0 insertions, 0 deletions