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| author | Francisco Iglesias <frasse.iglesias@gmail.com> | 2022-04-12 00:18:35 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-05-16 16:15:40 -0400 |
| commit | 8e58f6ec24f64b7d88f2b01d39049011f5097fae (patch) | |
| tree | 01a75c118270b5944ed60f28927898f51f1bc025 /include/hw/pci | |
| parent | 76b1b64370007234279ea4cc8b09c98cbd2523de (diff) | |
| download | qemu-8e58f6ec24f64b7d88f2b01d39049011f5097fae.zip qemu-8e58f6ec24f64b7d88f2b01d39049011f5097fae.tar.gz qemu-8e58f6ec24f64b7d88f2b01d39049011f5097fae.tar.bz2 | |
include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits). Below is the formula taken from Table
7-1 in [1].
"
Memory Address | PCI Express Configuration Space
A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8
"
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-2-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/pci')
| -rw-r--r-- | include/hw/pci/pcie_host.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index 076457b..b3c8ce9 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, /* * PCI express ECAM (Enhanced Configuration Address Mapping) format. * AKA mmcfg address - * bit 20 - 28: bus number + * bit 20 - 27: bus number * bit 15 - 19: device number * bit 12 - 14: function number * bit 0 - 11: offset in configuration space of a given device @@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, #define PCIE_MMCFG_SIZE_MAX (1ULL << 29) #define PCIE_MMCFG_SIZE_MIN (1ULL << 20) #define PCIE_MMCFG_BUS_BIT 20 -#define PCIE_MMCFG_BUS_MASK 0x1ff +#define PCIE_MMCFG_BUS_MASK 0xff #define PCIE_MMCFG_DEVFN_BIT 12 #define PCIE_MMCFG_DEVFN_MASK 0xff #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff |