diff options
| author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
| commit | c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664 (patch) | |
| tree | c96c7035f0de8f12cf38921f45ff7c8c93a6559f /include/hw/pci-host | |
| parent | 0aa2612a01f233a4a25fb89e8362baf6cf896be6 (diff) | |
| download | qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.zip qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.tar.gz qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.tar.bz2 | |
ppc/pnv: Add support for PQ offload on PHB5
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits have not been checked and performs the check
locally.
This configuration bit only applies to MSIs and LSIs are still checked
on the PHB to handle the assertion level.
PQ_disable enablement is a requirement for StoreEOI.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/pci-host')
| -rw-r--r-- | include/hw/pci-host/pnv_phb4_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h index 55df2c3..64f326b 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -225,6 +225,7 @@ /* Fundamental register set B */ #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 +#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) |