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| author | Steven Lee <steven_lee@aspeedtech.com> | 2022-05-02 17:03:02 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-05-02 17:03:02 +0200 |
| commit | dd7f19a963ca4e1bbfb65b72d555efcc507a2d78 (patch) | |
| tree | e6cefb9f1442711cf5ccaf6af08cd4f9bae8cd8a /include/hw/misc | |
| parent | f5643914a9e8f79c606a76e6a9d7ea82a3fc3e65 (diff) | |
| download | qemu-dd7f19a963ca4e1bbfb65b72d555efcc507a2d78.zip qemu-dd7f19a963ca4e1bbfb65b72d555efcc507a2d78.tar.gz qemu-dd7f19a963ca4e1bbfb65b72d555efcc507a2d78.tar.bz2 | |
hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function and an apb frequency calculation
function based on SCU200 register description in ast2600v11.pdf.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <20220315075753.8591-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/misc')
| -rw-r--r-- | include/hw/misc/aspeed_scu.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index c14aff2..8c4c8c8 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -56,6 +56,7 @@ struct AspeedSCUClass { const uint32_t *resets; uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); + uint32_t (*get_apb)(AspeedSCUState *s); uint32_t apb_divider; uint32_t nr_regs; const MemoryRegionOps *ops; @@ -316,4 +317,22 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2500_HW_STRAP_RESERVED1) +/* + * SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) + * + * 28:26 H-PLL Parameters + * 25 Enable H-PLL reset + * 24 Enable H-PLL bypass mode + * 23 Turn off H-PLL + * 22:19 H-PLL Post Divider (P) + * 18:13 H-PLL Numerator (M) + * 12:0 H-PLL Denumerator (N) + * + * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) + * + * The default frequency is 1200Mhz when CLKIN = 25MHz + */ +#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) +#define SCU_AST2600_H_PLL_OFF (0x1 << 23) + #endif /* ASPEED_SCU_H */ |