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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:38 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:38 +0100 |
| commit | 829f9fd394ab082753308cbda165c13eaf8fae49 (patch) | |
| tree | 328181ff25aab96c0527765a09e10ae4d385d1c5 /include/hw/misc/mps2-fpgaio.h | |
| parent | b9bc21ff9f9bb2d841adf1dc7f6f8ddfb9ab8b5e (diff) | |
| download | qemu-829f9fd394ab082753308cbda165c13eaf8fae49.zip qemu-829f9fd394ab082753308cbda165c13eaf8fae49.tar.gz qemu-829f9fd394ab082753308cbda165c13eaf8fae49.tar.bz2 | |
target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180820153020.21478-6-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/misc/mps2-fpgaio.h')
0 files changed, 0 insertions, 0 deletions