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| author | Cédric Le Goater <clg@kaod.org> | 2021-08-09 15:45:22 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-08-27 12:41:13 +1000 |
| commit | 363fd548abd5fbef040ee001c6694672bfb0d798 (patch) | |
| tree | e03daaa611fd19063da874b78dd2b53cd4a234ac /include/hw/mips | |
| parent | 1d76437b45ab9982307b95d325d627f7b6f06088 (diff) | |
| download | qemu-363fd548abd5fbef040ee001c6694672bfb0d798.zip qemu-363fd548abd5fbef040ee001c6694672bfb0d798.tar.gz qemu-363fd548abd5fbef040ee001c6694672bfb0d798.tar.bz2 | |
ppc: Add a POWER10 DD2 CPU
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
HAIL but since it does not break the modeling and that we don't plan
to support DD1, modify the LPCR mask of all the POWER10 family.
Setting the HAIL bit is a requirement to support the scv instruction
on PowerNV POWER10 platforms since glibc-2.33.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/mips')
0 files changed, 0 insertions, 0 deletions