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authorCao jin <caoj.fnst@cn.fujitsu.com>2016-05-17 09:41:18 +0800
committerMichael Tokarev <mjt@tls.msk.ru>2016-06-07 18:19:23 +0300
commit0668a06b81bb709b72aa816083227eb0d44b2ad6 (patch)
treec5d3c280b3c1f12e7b625f87629d19d92fbabd6d /include/hw/i386/ich9.h
parentbbd908025c530b57f57b5c5b739d53e28c1e59fc (diff)
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ICH9: fix typo
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'include/hw/i386/ich9.h')
-rw-r--r--include/hw/i386/ich9.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index d04dcdc..88233c3 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -35,7 +35,7 @@ typedef struct ICH9LPCState {
/* (pci device, intx) -> pirq
* In real chipset case, the unused slots are never used
- * as ICH9 supports only D25-D32 irq routing.
+ * as ICH9 supports only D25-D31 irq routing.
* On the other hand in qemu case, any slot/function can be populated
* via command line option.
* So fallback interrupt routing for any devices in any slots is necessary.
@@ -181,7 +181,7 @@ Object *ich9_lpc_find(void);
#define ICH9_SATA1_DEV 31
#define ICH9_SATA1_FUNC 2
-/* D30:F1 power management I/O registers
+/* D31:F0 power management I/O registers
offset from the address ICH9_LPC_PMBASE */
/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */