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| author | Peter Delevoryas <pdel@fb.com> | 2022-06-30 09:21:13 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-06-30 09:21:13 +0200 |
| commit | b582b7a191f23c3f862c3b3aef96d6136508c07f (patch) | |
| tree | 302168a5335701a24d57a157129999857bb4342d /include/hw/i2c/i2c.h | |
| parent | ceb3ff0e802bf7e373b1dbcff51541eefff25513 (diff) | |
| download | qemu-b582b7a191f23c3f862c3b3aef96d6136508c07f.zip qemu-b582b7a191f23c3f862c3b3aef96d6136508c07f.tar.gz qemu-b582b7a191f23c3f862c3b3aef96d6136508c07f.tar.bz2 | |
hw/i2c/aspeed: Fix DMA len write-enable bit handling
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I think we should be checking the write-enable bits on the incoming
value, not checking the register array. I'm not sure we're even writing
the write-enable bits to the register array, actually.
[1] https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148
Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-3-me@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/i2c/i2c.h')
0 files changed, 0 insertions, 0 deletions