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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-20 11:24:33 +0100 |
| commit | 6d0ed6ba6c1aa0201326d4f0072e91983495bb52 (patch) | |
| tree | 2b39b3812362f49728b6b6c85448eb705f6e09b9 /include/hw/dma | |
| parent | aa74e355f12438888eacdd8f3c2fc910b1b621a7 (diff) | |
| download | qemu-6d0ed6ba6c1aa0201326d4f0072e91983495bb52.zip qemu-6d0ed6ba6c1aa0201326d4f0072e91983495bb52.tar.gz qemu-6d0ed6ba6c1aa0201326d4f0072e91983495bb52.tar.bz2 | |
hw/dma/pl080: Support all three interrupt lines
The PL080 and PL081 have three outgoing interrupt lines:
* DMACINTERR signals DMA errors
* DMACINTTC is the DMA count interrupt
* DMACINTR is a combined interrupt, the logical OR of the other two
We currently only implement DMACINTR, because that's all the
realview and versatile boards needed, but the instances of the
PL081 in the MPS2 firmware images use all three interrupt lines.
Implement the missing DMACINTERR and DMACINTTC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'include/hw/dma')
| -rw-r--r-- | include/hw/dma/pl080.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h index 7deb46c..7c6a418 100644 --- a/include/hw/dma/pl080.h +++ b/include/hw/dma/pl080.h @@ -17,7 +17,9 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf * * QEMU interface: - * + sysbus IRQ: DMACINTR combined interrupt line + * + sysbus IRQ 0: DMACINTR combined interrupt line + * + sysbus IRQ 1: DMACINTERR error interrupt request + * + sysbus IRQ 2: DMACINTTC count interrupt request * + sysbus MMIO region 0: MemoryRegion for the device's registers */ @@ -57,6 +59,8 @@ typedef struct PL080State { /* Flag to avoid recursive DMA invocations. */ int running; qemu_irq irq; + qemu_irq interr; + qemu_irq inttc; } PL080State; #endif |