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| author | Ben Widawsky <ben.widawsky@intel.com> | 2022-04-29 15:40:37 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-05-13 06:13:36 -0400 |
| commit | 9dccb1216bf9d120579612979f4d58fd97bf0150 (patch) | |
| tree | cfdfd09fea6b114510008ed984d05e5595bfd37b /include/hw/cxl/cxl.h | |
| parent | 25a2e524e34e9a7cdf709a380b9deaada9dc4995 (diff) | |
| download | qemu-9dccb1216bf9d120579612979f4d58fd97bf0150.zip qemu-9dccb1216bf9d120579612979f4d58fd97bf0150.tar.gz qemu-9dccb1216bf9d120579612979f4d58fd97bf0150.tar.bz2 | |
hw/pci/cxl: Create a CXL bus type
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/cxl/cxl.h')
0 files changed, 0 insertions, 0 deletions