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| author | Havard Skinnemoen <hskinnemoen@google.com> | 2020-09-10 22:20:55 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-14 14:24:59 +0100 |
| commit | c752bb079beb57a8527e55859ce4c416fb1663c3 (patch) | |
| tree | 46149cb1a7a73df44d6c3e1a4e73e10a3864ffc7 /include/hw/arm/npcm7xx.h | |
| parent | 4e89ccd685a381981c9b295888eb269b67c3320b (diff) | |
| download | qemu-c752bb079beb57a8527e55859ce4c416fb1663c3.zip qemu-c752bb079beb57a8527e55859ce4c416fb1663c3.tar.gz qemu-c752bb079beb57a8527e55859ce4c416fb1663c3.tar.bz2 | |
hw/nvram: NPCM7xx OTP device model
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-9-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/npcm7xx.h')
| -rw-r--r-- | include/hw/arm/npcm7xx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index ba74958..5816a07 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" +#include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "target/arm/cpu.h" @@ -68,6 +69,8 @@ typedef struct NPCM7xxState { NPCM7xxGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; + NPCM7xxOTPState key_storage; + NPCM7xxOTPState fuse_array; } NPCM7xxState; #define TYPE_NPCM7XX "npcm7xx" |