aboutsummaryrefslogtreecommitdiff
path: root/include/fpu
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2021-10-29 10:59:09 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-10-29 10:59:09 -0700
commit6450ce5634a57e57ee8bb790c080fc7636678f3d (patch)
tree24f52476f9f0bdacc83646f4e3aefe3f230f1807 /include/fpu
parenta92cecba2791cd408d2bca04ce181dc2abaf9695 (diff)
parent15161e425ee1bb1180f9cec574cda44fb10c0931 (diff)
downloadqemu-6450ce5634a57e57ee8bb790c080fc7636678f3d.zip
qemu-6450ce5634a57e57ee8bb790c080fc7636678f3d.tar.gz
qemu-6450ce5634a57e57ee8bb790c080fc7636678f3d.tar.bz2
Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20211029-1' into staging
Fifth RISC-V PR for QEMU 6.2 - Use a shared PLIC config helper function - Fixup the OpenTitan PLIC configuration - Add support for the experimental J extension - Update the fmin/fmax handling - Fixup VS interrupt forwarding # gpg: Signature made Fri 29 Oct 2021 12:03:47 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211029-1: target/riscv: change the api for RVF/RVD fmin/fmax softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin target/riscv: remove force HS exception target/riscv: fix VS interrupts forwarding to HS target/riscv: Allow experimental J-ext to be turned on target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions target/riscv: Print new PM CSRs in QEMU logs target/riscv: Add J extension state description target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Add J-extension into RISC-V hw/riscv: opentitan: Fixup the PLIC context addresses hw/riscv: virt: Use the PLIC config helper function hw/riscv: microchip_pfsoc: Use the PLIC config helper function hw/riscv: sifive_u: Use the PLIC config helper function hw/riscv: boot: Add a PLIC config string function hw/riscv: virt: Don't use a macro for the PLIC configuration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/fpu')
-rw-r--r--include/fpu/softfloat.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index ec7dca0..a249991 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -243,6 +243,8 @@ float16 float16_minnum(float16, float16, float_status *status);
float16 float16_maxnum(float16, float16, float_status *status);
float16 float16_minnummag(float16, float16, float_status *status);
float16 float16_maxnummag(float16, float16, float_status *status);
+float16 float16_minimum_number(float16, float16, float_status *status);
+float16 float16_maximum_number(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
@@ -422,6 +424,8 @@ bfloat16 bfloat16_minnum(bfloat16, bfloat16, float_status *status);
bfloat16 bfloat16_maxnum(bfloat16, bfloat16, float_status *status);
bfloat16 bfloat16_minnummag(bfloat16, bfloat16, float_status *status);
bfloat16 bfloat16_maxnummag(bfloat16, bfloat16, float_status *status);
+bfloat16 bfloat16_minimum_number(bfloat16, bfloat16, float_status *status);
+bfloat16 bfloat16_maximum_number(bfloat16, bfloat16, float_status *status);
bfloat16 bfloat16_sqrt(bfloat16, float_status *status);
FloatRelation bfloat16_compare(bfloat16, bfloat16, float_status *status);
FloatRelation bfloat16_compare_quiet(bfloat16, bfloat16, float_status *status);
@@ -589,6 +593,8 @@ float32 float32_minnum(float32, float32, float_status *status);
float32 float32_maxnum(float32, float32, float_status *status);
float32 float32_minnummag(float32, float32, float_status *status);
float32 float32_maxnummag(float32, float32, float_status *status);
+float32 float32_minimum_number(float32, float32, float_status *status);
+float32 float32_maximum_number(float32, float32, float_status *status);
bool float32_is_quiet_nan(float32, float_status *status);
bool float32_is_signaling_nan(float32, float_status *status);
float32 float32_silence_nan(float32, float_status *status);
@@ -778,6 +784,8 @@ float64 float64_minnum(float64, float64, float_status *status);
float64 float64_maxnum(float64, float64, float_status *status);
float64 float64_minnummag(float64, float64, float_status *status);
float64 float64_maxnummag(float64, float64, float_status *status);
+float64 float64_minimum_number(float64, float64, float_status *status);
+float64 float64_maximum_number(float64, float64, float_status *status);
bool float64_is_quiet_nan(float64 a, float_status *status);
bool float64_is_signaling_nan(float64, float_status *status);
float64 float64_silence_nan(float64, float_status *status);
@@ -1210,6 +1218,8 @@ float128 float128_minnum(float128, float128, float_status *status);
float128 float128_maxnum(float128, float128, float_status *status);
float128 float128_minnummag(float128, float128, float_status *status);
float128 float128_maxnummag(float128, float128, float_status *status);
+float128 float128_minimum_number(float128, float128, float_status *status);
+float128 float128_maximum_number(float128, float128, float_status *status);
bool float128_is_quiet_nan(float128, float_status *status);
bool float128_is_signaling_nan(float128, float_status *status);
float128 float128_silence_nan(float128, float_status *status);