diff options
| author | Bharata B Rao <bharata@linux.vnet.ibm.com> | 2017-02-10 12:53:05 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-02-22 11:28:28 +1100 |
| commit | 9ee6f678f473007e252934d6acd09c24490d9d42 (patch) | |
| tree | ea047e7fd74f4518830d8bb3a456088dce977fea /include/fpu | |
| parent | 5b929608b94fc3ee4104553f961b6b1fae3d7b88 (diff) | |
| download | qemu-9ee6f678f473007e252934d6acd09c24490d9d42.zip qemu-9ee6f678f473007e252934d6acd09c24490d9d42.tar.gz qemu-9ee6f678f473007e252934d6acd09c24490d9d42.tar.bz2 | |
softfloat: Add round-to-odd rounding mode
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/fpu')
| -rw-r--r-- | include/fpu/softfloat.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 842ec6b..8a39028 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -180,6 +180,8 @@ enum { float_round_up = 2, float_round_to_zero = 3, float_round_ties_away = 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value */ + float_round_to_odd = 5, }; /*---------------------------------------------------------------------------- |