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authorCédric Le Goater <clg@kaod.org>2022-03-02 06:51:38 +0100
committerCédric Le Goater <clg@kaod.org>2022-03-02 06:51:38 +0100
commitf8a233dedf2560d7d592dab347ddf2a58e8a98db (patch)
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parent604d00c76fdd7dfcaa2bf8515615ad129a4fdcc4 (diff)
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ppc/xive2: Introduce a XIVE2 core framework
The XIVE2 interrupt controller of the POWER10 processor as the same logic as on POWER9 but its SW interface has been largely reworked. The interrupt controller has a new register interface, different BARs, extra VSDs. These will be described when we add the device model for the baremetal machine. The XIVE internal structures for the EAS, END, NVT have different layouts which is a problem for the current core XIVE framework. To avoid adding too much complexity in the XIVE models, a new XIVE2 core framework is introduced. It duplicates the models which are closely linked to the XIVE internal structures : Xive2Router and Xive2ENDSource and reuses the XiveSource, XivePresenter, XiveTCTX models, as they are more generic. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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