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author | Alexander Graf <agraf@suse.de> | 2013-12-11 14:17:44 +0100 |
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committer | Alexander Graf <agraf@suse.de> | 2013-12-20 01:58:03 +0100 |
commit | 582b55a96ac4f66cea64d82e47651bd5ef38a8ec (patch) | |
tree | abcae368c4aa57f047e23b76fb9bd25a19a33bcc /include/exec/cpu-common.h | |
parent | 3978b863a5d8ac1c02848bf57d0a7f7067826a8a (diff) | |
download | qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.zip qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.tar.gz qemu-582b55a96ac4f66cea64d82e47651bd5ef38a8ec.tar.bz2 |
roms: Flush icache when writing roms to guest memory
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to ensure that after reboot we
don't happen to execute stale bits from the instruction cache.
So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.
This fixes random reboot issues on e5500 (booke ppc) for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'include/exec/cpu-common.h')
-rw-r--r-- | include/exec/cpu-common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index e4996e1..8f33122 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -110,6 +110,7 @@ void stq_phys(hwaddr addr, uint64_t val); void cpu_physical_memory_write_rom(hwaddr addr, const uint8_t *buf, int len); +void cpu_flush_icache_range(hwaddr start, int len); extern struct MemoryRegion io_mem_rom; extern struct MemoryRegion io_mem_notdirty; |