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| author | Cédric Le Goater <clg@redhat.com> | 2024-05-07 16:12:12 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2024-06-16 21:08:54 +0200 |
| commit | ee48fef06c034ff245db9e553dcf0f1262f97bd2 (patch) | |
| tree | 7f246e0d00c0cc17feceea240db21005570efd30 /hw | |
| parent | 05ad1440b8428b0ade9b8e5c01469adb8fbf83e3 (diff) | |
| download | qemu-ee48fef06c034ff245db9e553dcf0f1262f97bd2.zip qemu-ee48fef06c034ff245db9e553dcf0f1262f97bd2.tar.gz qemu-ee48fef06c034ff245db9e553dcf0f1262f97bd2.tar.bz2 | |
aspeed/smc: Reintroduce "dram-base" property for AST2700
The Aspeed SMC device model use to have a 'sdram_base' property. It
was removed by commit d177892d4a48 ("aspeed/smc: Remove unused
"sdram-base" property") because previous changes simplified the DMA
transaction model to use an offset in RAM and not the physical
address.
The AST2700 SoC has larger address space (64-bit) and a new register
DMA DRAM Side Address High Part (0x7C) is introduced to deal with the
high bits of the DMA address. To be able to compute the offset of the
DMA transaction, as done on the other SoCs, we will need to know where
the DRAM is mapped in the address space. Re-introduce a "dram-base"
property to hold this value.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 6e1a84c..7075bc9 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1220,6 +1220,7 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), + DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), |