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| author | Ramon Fried <rfried.dev@gmail.com> | 2020-04-17 20:17:36 +0300 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-30 15:35:41 +0100 |
| commit | f1e7cb1388e46eac8285854af2abdfde41ffa226 (patch) | |
| tree | d459b573921c47214531ba3cd016aa0033c90459 /hw | |
| parent | 681b5bc32322fd0ff4338c550ec24612512d1a2e (diff) | |
| download | qemu-f1e7cb1388e46eac8285854af2abdfde41ffa226.zip qemu-f1e7cb1388e46eac8285854af2abdfde41ffa226.tar.gz qemu-f1e7cb1388e46eac8285854af2abdfde41ffa226.tar.bz2 | |
Cadence: gem: fix wraparound in 64bit descriptors
Wraparound of TX descriptor cyclic buffer only updated
the low 32 bits of the descriptor.
Fix that by checking if we're working with 64bit descriptors.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200417171736.441607-1-rfried.dev@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/net/cadence_gem.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 51ec5a0..b7b7985 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1238,7 +1238,14 @@ static void gem_transmit(CadenceGEMState *s) /* read next descriptor */ if (tx_desc_get_wrap(desc)) { tx_desc_set_last(desc); - packet_desc_addr = s->regs[GEM_TXQBASE]; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + packet_desc_addr = s->regs[GEM_TBQPH]; + packet_desc_addr <<= 32; + } else { + packet_desc_addr = 0; + } + packet_desc_addr |= s->regs[GEM_TXQBASE]; } else { packet_desc_addr += 4 * gem_get_desc_len(s, false); } |