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| author | Corey Minyard <cminyard@mvista.com> | 2016-10-24 10:42:33 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-24 16:48:02 +0100 |
| commit | cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f (patch) | |
| tree | f19623fb6ecd678d87d0cbd769ba8d979aeace2a /hw | |
| parent | 19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e (diff) | |
| download | qemu-cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f.zip qemu-cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f.tar.gz qemu-cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f.tar.bz2 | |
i2c: Add asserts for second smbus i2c_start_transfer()
Some SMBus operations restart the transfer to convert from
write to read mode without an intervening i2c_end_transfer().
The second call cannot fail, so the return code is unchecked,
but this causes Coverity to complain. So add some asserts
and documentation about this.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/i2c/core.c | 7 | ||||
| -rw-r--r-- | hw/i2c/smbus.c | 12 |
2 files changed, 15 insertions, 4 deletions
diff --git a/hw/i2c/core.c b/hw/i2c/core.c index bd8f167..abd4c4c 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -88,7 +88,12 @@ int i2c_bus_busy(I2CBus *bus) return !QLIST_EMPTY(&bus->current_devs); } -/* Returns non-zero if the address is not valid. */ +/* + * Returns non-zero if the address is not valid. If this is called + * again without an intervening i2c_end_transfer(), like in the SMBus + * case where the operation is switched from write to read, this + * function will not rescan the bus and thus cannot fail. + */ /* TODO: Make this handle multiple masters. */ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv) { diff --git a/hw/i2c/smbus.c b/hw/i2c/smbus.c index 3979b3d..5b4dd3e 100644 --- a/hw/i2c/smbus.c +++ b/hw/i2c/smbus.c @@ -248,7 +248,9 @@ int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command) return -1; } i2c_send(bus, command); - i2c_start_transfer(bus, addr, 1); + if (i2c_start_transfer(bus, addr, 1)) { + assert(0); + } data = i2c_recv(bus); i2c_nack(bus); i2c_end_transfer(bus); @@ -273,7 +275,9 @@ int smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command) return -1; } i2c_send(bus, command); - i2c_start_transfer(bus, addr, 1); + if (i2c_start_transfer(bus, addr, 1)) { + assert(0); + } data = i2c_recv(bus); data |= i2c_recv(bus) << 8; i2c_nack(bus); @@ -302,7 +306,9 @@ int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data) return -1; } i2c_send(bus, command); - i2c_start_transfer(bus, addr, 1); + if (i2c_start_transfer(bus, addr, 1)) { + assert(0); + } len = i2c_recv(bus); if (len > 32) { len = 0; |