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author | Bin Meng <bmeng.cn@gmail.com> | 2021-09-13 16:07:21 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-13 16:07:21 +0100 |
commit | 7956a8f5dd702adf351575b2aee9dbd99001b61f (patch) | |
tree | 9ec6af97062fa6b7d6161dcd25e3c76b043081ae /hw | |
parent | 983f4adf364628bf1e75f99d85a47a803d2e2dce (diff) | |
download | qemu-7956a8f5dd702adf351575b2aee9dbd99001b61f.zip qemu-7956a8f5dd702adf351575b2aee9dbd99001b61f.tar.gz qemu-7956a8f5dd702adf351575b2aee9dbd99001b61f.tar.bz2 |
hw/char: cadence_uart: Convert to memop_with_attrs() ops
This converts uart_read() and uart_write() to memop_with_attrs() ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-5-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/char/cadence_uart.c | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fff8be3..8bcf2b7 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -411,15 +411,15 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c) uart_update_status(s); } -static void uart_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) +static MemTxResult uart_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size, MemTxAttrs attrs) { CadenceUARTState *s = opaque; DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { - return; + return MEMTX_DECODE_ERROR; } switch (offset) { case R_IER: /* ier (wts imr) */ @@ -466,30 +466,34 @@ static void uart_write(void *opaque, hwaddr offset, break; } uart_update_status(s); + + return MEMTX_OK; } -static uint64_t uart_read(void *opaque, hwaddr offset, - unsigned size) +static MemTxResult uart_read(void *opaque, hwaddr offset, + uint64_t *value, unsigned size, MemTxAttrs attrs) { CadenceUARTState *s = opaque; uint32_t c = 0; offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { - c = 0; - } else if (offset == R_TX_RX) { + return MEMTX_DECODE_ERROR; + } + if (offset == R_TX_RX) { uart_read_rx_fifo(s, &c); } else { - c = s->r[offset]; + c = s->r[offset]; } DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); - return c; + *value = c; + return MEMTX_OK; } static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, + .read_with_attrs = uart_read, + .write_with_attrs = uart_write, .endianness = DEVICE_NATIVE_ENDIAN, }; |