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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2020-07-21 21:37:42 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-22 09:39:46 -0700 |
| commit | 3e09396e36dff4234afd6f6fd51861949be383e1 (patch) | |
| tree | 85b2f145299fedaff790c06c74445c6d020003fb /hw | |
| parent | eabfeb0cb9e054108b3e29a3a85363b3d80d9c38 (diff) | |
| download | qemu-3e09396e36dff4234afd6f6fd51861949be383e1.zip qemu-3e09396e36dff4234afd6f6fd51861949be383e1.tar.gz qemu-3e09396e36dff4234afd6f6fd51861949be383e1.tar.bz2 | |
target/riscv: fix vector index load/store constraints
Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.
And this constraint has been added to the v0.8 spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw')
0 files changed, 0 insertions, 0 deletions