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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-07-17 15:48:27 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-07-17 15:48:48 +0100 |
| commit | 08572022e5b743f7f52ed99cd1f4e50f77ff0038 (patch) | |
| tree | 5b102fdc0e98041fb4bc61a7b3d1c3e2513b6fca /hw | |
| parent | f44ccac2c0c4c8dc8007b8647e50dcfb16fe7cce (diff) | |
| parent | c2c1c4a35c7c2b1a4140b0942b9797c857e476a4 (diff) | |
| download | qemu-08572022e5b743f7f52ed99cd1f4e50f77ff0038.zip qemu-08572022e5b743f7f52ed99cd1f4e50f77ff0038.tar.gz qemu-08572022e5b743f7f52ed99cd1f4e50f77ff0038.tar.bz2 | |
Merge tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/sbsa-ref: set 'slots' property of xhci
* linux-user: Remove pointless NULL check in clock_adjtime handling
* ptw: Fix S1_ptw_translate() debug path
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
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# gpg: Signature made Mon 17 Jul 2023 01:47:01 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
target/arm: Fix S1_ptw_translate() debug path
target/arm/ptw.c: Add comments to S1Translate struct fields
linux-user: Remove pointless NULL check in clock_adjtime handling
hw/arm/sbsa-ref: set 'slots' property of xhci
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/arm/sbsa-ref.c | 1 | ||||
| -rw-r--r-- | hw/nvram/xlnx-efuse.c | 11 |
2 files changed, 10 insertions, 2 deletions
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 64e1cbc..bc89eb4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -611,6 +611,7 @@ static void create_xhci(const SBSAMachineState *sms) hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; int irq = sbsa_ref_irqmap[SBSA_XHCI]; DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); + qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index fdfffaa..655c40b 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -143,6 +143,8 @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) { + uint32_t set, *row; + if (efuse_ro_bits_find(s, bit)) { g_autofree char *path = object_get_canonical_path(OBJECT(s)); @@ -152,8 +154,13 @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) return false; } - s->fuse32[bit / 32] |= 1 << (bit % 32); - efuse_bdrv_sync(s, bit); + /* Avoid back-end write unless there is a real update */ + row = &s->fuse32[bit / 32]; + set = 1 << (bit % 32); + if (!(set & *row)) { + *row |= set; + efuse_bdrv_sync(s, bit); + } return true; } |