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author | Peter Maydell <peter.maydell@linaro.org> | 2020-04-03 10:07:27 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-03 10:07:27 +0100 |
commit | f2a8261110c32c4dccd84e774d8dd7a0524e00fb (patch) | |
tree | 88c62d86316132f701dc2f181cae437fa90e2e40 /hw | |
parent | 5142ca078d1cbc0f77b0f385d28cdb3e504e62bd (diff) | |
parent | d965dc35592d24c0c1519f1c566223c6277cb80e (diff) | |
download | qemu-f2a8261110c32c4dccd84e774d8dd7a0524e00fb.zip qemu-f2a8261110c32c4dccd84e774d8dd7a0524e00fb.tar.gz qemu-f2a8261110c32c4dccd84e774d8dd7a0524e00fb.tar.bz2 |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging
x86 queue for -rc2
Fixes:
* EPYC CPU model APIC ID topology fixes (Babu Moger)
* Fix crash when enabling intel-pt on older machine types
(Luwei Kang)
* Add missing ARCH_CAPABILITIES bits to Icelake-Server CPU model
(Xiaoyao Li)
# gpg: Signature made Thu 02 Apr 2020 23:18:30 BST
# gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg: issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/x86-next-pull-request:
target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model
target/i386: set the CPUID level to 0x14 on old machine-type
i386: Fix pkg_id offset for EPYC cpu models
target/i386: Enable new apic id encoding for EPYC based cpus models
hw/i386: Move arch_id decode inside x86_cpus_init
i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition
hw/i386: Introduce apicid functions inside X86MachineState
target/i386: Cleanup and use the EPYC mode topology functions
hw/386: Add EPYC mode topology decoding functions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/i386/pc.c | 7 | ||||
-rw-r--r-- | hw/i386/x86.c | 42 |
2 files changed, 39 insertions, 10 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 0bf0aac..5143c51 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1526,6 +1526,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, env->nr_dies = x86ms->smp_dies; env->nr_nodes = topo_info.nodes_per_pkg; + env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info); /* * If APIC ID is not set, @@ -1580,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id = cpu->die_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms = MACHINE(pcms); - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -1608,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 6ca3cf9..b827700 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -69,6 +69,22 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info, } /* + * Set up with the new EPYC topology handlers + * + * AMD uses different apic id encoding for EPYC based cpus. Override + * the default topo handlers with EPYC encoding handlers. + */ +static void x86_set_epyc_topo_handlers(MachineState *machine) +{ + X86MachineState *x86ms = X86_MACHINE(machine); + + x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc; + x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc; + x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc; + x86ms->apicid_pkg_offset = apicid_pkg_offset_epyc; +} + +/* * Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index @@ -86,7 +102,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, init_topo_info(&topo_info, x86ms); - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); + correct_id = x86ms->apicid_from_cpu_idx(&topo_info, cpu_index); if (x86mc->compat_apic_id_mode) { if (cpu_index != correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -121,6 +137,11 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) MachineState *ms = MACHINE(x86ms); MachineClass *mc = MACHINE_GET_CLASS(x86ms); + /* Check for apicid encoding */ + if (cpu_x86_use_epyc_apic_id_encoding(ms->cpu_type)) { + x86_set_epyc_topo_handlers(ms); + } + x86_cpu_set_default_version(default_cpu_version); /* @@ -134,6 +155,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, ms->smp.max_cpus - 1) + 1; possible_cpus = mc->possible_cpu_arch_ids(ms); + + for (i = 0; i < ms->possible_cpus->len; i++) { + ms->possible_cpus->cpus[i].arch_id = + x86_cpu_apic_id_from_index(x86ms, i); + } + for (i = 0; i < ms->smp.cpus; i++) { x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); } @@ -158,8 +185,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) init_topo_info(&topo_info, x86ms); assert(idx < ms->possible_cpus->len); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } @@ -190,10 +216,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].type = ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count = 1; - ms->possible_cpus->cpus[i].arch_id = - x86_cpu_apic_id_from_index(x86ms, i); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, i, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; if (x86ms->smp_dies > 1) { @@ -937,6 +960,11 @@ static void x86_machine_initfn(Object *obj) x86ms->acpi = ON_OFF_AUTO_AUTO; x86ms->max_ram_below_4g = 0; /* use default */ x86ms->smp_dies = 1; + + x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; + x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid; + x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids; + x86ms->apicid_pkg_offset = apicid_pkg_offset; } static void x86_machine_class_init(ObjectClass *oc, void *data) |