aboutsummaryrefslogtreecommitdiff
path: root/hw
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2019-02-01 14:55:41 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-01 14:55:41 +0000
commit3693f217d38f053fa5a7fcd2841c07926c026218 (patch)
tree6b871f3400bc5ca86da8931abc95035424a63b5d /hw
parent287a7f6e39cfc44a39909862365fddfc90778968 (diff)
downloadqemu-3693f217d38f053fa5a7fcd2841c07926c026218.zip
qemu-3693f217d38f053fa5a7fcd2841c07926c026218.tar.gz
qemu-3693f217d38f053fa5a7fcd2841c07926c026218.tar.bz2
armv7m: Don't assume the NVIC's CPU is CPU 0
Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-2-peter.maydell@linaro.org
Diffstat (limited to 'hw')
-rw-r--r--hw/arm/armv7m.c6
-rw-r--r--hw/intc/armv7m_nvic.c3
2 files changed, 5 insertions, 4 deletions
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index f444652..f9aa83d 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
}
- /* Tell the CPU where the NVIC is; it will fail realize if it doesn't
- * have one.
+ /*
+ * Tell the CPU where the NVIC is; it will fail realize if it doesn't
+ * have one. Similarly, tell the NVIC where its CPU is.
*/
s->cpu->env.nvic = &s->nvic;
+ s->nvic.cpu = s->cpu;
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
if (err != NULL) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 0beefb0..790a3d9 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
int regionlen;
- s->cpu = ARM_CPU(qemu_get_cpu(0));
-
+ /* The armv7m container object will have set our CPU pointer */
if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
error_setg(errp, "The NVIC can only be used with a Cortex-M CPU");
return;