PowerPC system emulation fixes (Jocelyn Mayer)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@722 c046a42c-6fe2-441c-8c8c-71466251a162

7 files changed, 1676 insertions, 253 deletions

diff --git a/hw/fdc.c b/hw/fdc.c
index 7d7837b..0de5578 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -83,7 +83,6 @@ typedef struct fdrive_t {
     uint8_t dir;              /* Direction              */
     uint8_t rw;               /* Read/write             */
     /* Media */
-    fdisk_type_t disk;        /* Disk type              */
     fdisk_flags_t flags;
     uint8_t last_sect;        /* Nb sector per track    */
     uint8_t max_track;        /* Nb of tracks           */
@@ -102,7 +101,6 @@ static void fd_init (fdrive_t *drv, BlockDriverState *bs)
     drv->drflags = 0;
     drv->perpendicular = 0;
     /* Disk */
-    drv->disk = FDRIVE_DISK_NONE;
     drv->last_sect = 0;
     drv->max_track = 0;
 }
@@ -171,26 +169,113 @@ static void fd_recalibrate (fdrive_t *drv)
     drv->rw = 0;
 }
 
+/* Recognize floppy formats */
+typedef struct fd_format_t {
+    fdrive_type_t drive;
+    fdisk_type_t  disk;
+    uint8_t last_sect;
+    uint8_t max_track;
+    uint8_t max_head;
+    const unsigned char *str;
+} fd_format_t;
+
+static fd_format_t fd_formats[] = {
+    /* First entry is default format */
+    /* 1.44 MB 3"1/2 floppy disks */
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
+    /* 2.88 MB 3"1/2 floppy disks */
+    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
+    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
+    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
+    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
+    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
+    /* 720 kB 3"1/2 floppy disks */
+    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
+    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
+    /* 1.2 MB 5"1/4 floppy disks */
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
+    /* 720 kB 5"1/4 floppy disks */
+    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
+    /* 360 kB 5"1/4 floppy disks */
+    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
+    /* 320 kB 5"1/4 floppy disks */ 
+    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
+    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
+    /* 360 kB must match 5"1/4 better than 3"1/2... */
+    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
+    /* end */
+    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
+};
+
 /* Revalidate a disk drive after a disk change */
 static void fd_revalidate (fdrive_t *drv)
 {
-    int64_t nb_sectors;
+    fd_format_t *parse;
+    int64_t nb_sectors, size;
+    int i, first_match, match;
     int nb_heads, max_track, last_sect, ro;
 
     FLOPPY_DPRINTF("revalidate\n");
     drv->drflags &= ~FDRIVE_REVALIDATE;
-
-    /* if no drive present, cannot do more */
-    if (!drv->bs)
-        return;
-
-    if (bdrv_is_inserted(drv->bs)) {
+    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
 	ro = bdrv_is_read_only(drv->bs);
-	bdrv_get_geometry_hint(drv->bs, &max_track, &nb_heads, &last_sect);
+	bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
 	if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
-	    drv->disk = FDRIVE_DISK_USER;
 	    printf("User defined disk (%d %d %d)",
 		   nb_heads - 1, max_track, last_sect);
+	} else {
+	    bdrv_get_geometry(drv->bs, &nb_sectors);
+	    match = -1;
+	    first_match = -1;
+	    for (i = 0;; i++) {
+		parse = &fd_formats[i];
+		if (parse->drive == FDRIVE_DRV_NONE)
+		    break;
+		if (drv->drive == parse->drive ||
+		    drv->drive == FDRIVE_DRV_NONE) {
+		    size = (parse->max_head + 1) * parse->max_track *
+			parse->last_sect;
+		    if (nb_sectors == size) {
+			match = i;
+			break;
+		    }
+		    if (first_match == -1)
+			first_match = i;
+		}
+	    }
+	    if (match == -1) {
+		if (first_match == -1)
+		    match = 1;
+		else
+		    match = first_match;
+		parse = &fd_formats[match];
+	    }
+	    nb_heads = parse->max_head + 1;
+	    max_track = parse->max_track;
+	    last_sect = parse->last_sect;
+	    drv->drive = parse->drive;
+	    printf("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
+		   nb_heads, max_track, last_sect, ro ? "ro" : "rw");
+	}
 	    if (nb_heads == 1) {
 		drv->flags &= ~FDISK_DBL_SIDES;
 	    } else {
@@ -198,236 +283,9 @@ static void fd_revalidate (fdrive_t *drv)
 	    }
 	    drv->max_track = max_track;
 	    drv->last_sect = last_sect;
-	} else {
-        bdrv_get_geometry(drv->bs, &nb_sectors);
-	    switch (nb_sectors) {
-            /* 2.88 MB 3"1/2 drive disks */
-	    case 7680:
-		printf("3.84 Mb 3\"1/2 disk (1 80 48)");
-		drv->drive = FDRIVE_DRV_288;
-		drv->disk = FDRIVE_DISK_288;
-		drv->last_sect = 48;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 7040:
-		printf("3.52 Mb 3\"1/2 disk (1 80 44)");
-		drv->drive = FDRIVE_DRV_288;
-		drv->disk = FDRIVE_DISK_288;
-		drv->last_sect = 44;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 6400:
-		printf("3.2 Mb 3\"1/2 disk (1 80 40)");
-		drv->drive = FDRIVE_DRV_288;
-		drv->disk = FDRIVE_DISK_288;
-		drv->last_sect = 40;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 6240:
-		printf("3.12 Mb 3\"1/2 disk (1 80 39)");
-		drv->drive = FDRIVE_DRV_288;
-		drv->disk = FDRIVE_DISK_288;
-		drv->last_sect = 39;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 5760:
-		printf("2.88 Mb 3\"1/2 disk (1 80 36)");
-		drv->drive = FDRIVE_DRV_288;
-            drv->disk = FDRIVE_DISK_288;
-            drv->last_sect = 36;
-            drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-
-            /* 1.44 MB 3"1/2 drive disks */
-	    case 3840:
-		printf("1.92 Mb 3\"1/2 disk (1 80 24)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 24;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3680:
-		printf("1.84 Mb 3\"1/2 disk (1 80 23)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 23;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3520:
-		printf("1.76 Mb 3\"1/2 disk (1 80 22)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 22;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3486:
-		printf("1.74 Mb 3\"1/2 disk (1 83 21)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 21;
-		drv->max_track = 83;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3444:
-		printf("1.72 Mb 3\"1/2 disk (1 82 21)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 21;
-		drv->max_track = 82;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3360:
-		printf("1.68 Mb 3\"1/2 disk (1 80 21)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 21;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 3200:
-		printf("1.6 Mb 3\"1/2 disk (1 80 20)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_144;
-		drv->last_sect = 20;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 2880:
-	    default:
-		printf("1.44 Mb 3\"1/2 disk (1 80 18)");
-		drv->drive = FDRIVE_DRV_144;
-            drv->disk = FDRIVE_DISK_144;
-            drv->last_sect = 18;
-            drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-
-            /* 720 kB 3"1/2 drive disks */
-	    case 2240:
-		printf("1.12 Mb 3\"1/2 disk (1 80 14)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_720;
-		drv->last_sect = 14;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 2080:
-		printf("1.04 Mb 3\"1/2 disk (1 80 13)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_720;
-		drv->last_sect = 13;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 1660:
-		printf("830 kb 3\"1/2 disk (1 83 10)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_720;
-		drv->last_sect = 10;
-		drv->max_track = 83;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 1640:
-		printf("820 kb 3\"1/2 disk (1 82 10)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_720;
-		drv->last_sect = 10;
-		drv->max_track = 82;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 1600:
-		printf("800 kb 3\"1/2 disk (1 80 10)");
-		drv->drive = FDRIVE_DRV_144;
-		drv->disk = FDRIVE_DISK_720;
-		drv->last_sect = 10;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 1440:
-		printf("720 kb 3\"1/2 disk (1 80 9)");
-		drv->drive = FDRIVE_DRV_144;
-            drv->disk = FDRIVE_DISK_720;
-            drv->last_sect = 9;
-            drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-
-	    /* 1.2 MB 5"1/4 drive disks */
-	    case 2988:
-		printf("1.49 Mb 5\"1/4 disk (1 83 18)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 18;
-		drv->max_track = 83;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 2952:
-		printf("1.48 Mb 5\"1/4 disk (1 82 18)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 18;
-		drv->max_track = 82;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-	    case 2400:
-		printf("1.2 Mb 5\"1/4 disk (1 80 15)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 15;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-
-	    case 1760:
-		printf("880 kb 5\"1/4 disk (1 80 11)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 11;
-		drv->max_track = 80;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-
-	    /* 360 kB 5"1/4 drive disks */
-	    case 840:
-		/* 420 kB 5"1/4 disk */
-		printf("420 kb 5\"1/4 disk (1 42 10)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 10;
-		drv->max_track = 42;
-		drv->flags |= FDISK_DBL_SIDES;
-	    case 820:
-		/* 410 kB 5"1/4 disk */
-		printf("410 kb 5\"1/4 disk (1 41 10)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 10;
-		drv->max_track = 41;
-		drv->flags |= FDISK_DBL_SIDES;
-	    case 720:
-		/* 360 kB 5"1/4 disk */
-		printf("360 kb 5\"1/4 disk (1 40 9)");
-		drv->drive = FDRIVE_DRV_120;
-		drv->disk = FDRIVE_DISK_144; /* ? */
-		drv->last_sect = 9;
-		drv->max_track = 40;
-		drv->flags |= FDISK_DBL_SIDES;
-		break;
-        }
-	    printf(" %s\n", ro == 0 ? "rw" : "ro");
-	}
 	drv->ro = ro;
     } else {
 	printf("No disk in drive\n");
-        drv->disk = FDRIVE_DISK_NONE;
         drv->last_sect = 0;
 	drv->max_track = 0;
 	drv->flags &= ~FDISK_DBL_SIDES;
@@ -544,20 +402,29 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg)
     fdctrl_t *fdctrl = opaque;
     uint32_t retval;
 
-    if (reg == fdctrl->io_base + 0x01)
+    switch (reg & 0x07) {
+    case 0x01:
 	retval = fdctrl_read_statusB(fdctrl);
-    else if (reg == fdctrl->io_base + 0x02)
+	break;
+    case 0x02:
 	retval = fdctrl_read_dor(fdctrl);
-    else if (reg == fdctrl->io_base + 0x03)
+	break;
+    case 0x03:
         retval = fdctrl_read_tape(fdctrl);
-    else if (reg == fdctrl->io_base + 0x04)
+	break;
+    case 0x04:
         retval = fdctrl_read_main_status(fdctrl);
-    else if (reg == fdctrl->io_base + 0x05)
+	break;
+    case 0x05:
         retval = fdctrl_read_data(fdctrl);
-    else if (reg == fdctrl->io_base + 0x07)
+	break;
+    case 0x07:
         retval = fdctrl_read_dir(fdctrl);
-    else 
+	break;
+    default:
 	retval = (uint32_t)(-1);
+	break;
+    }
 
     return retval;
 }
@@ -566,14 +433,22 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
 {
     fdctrl_t *fdctrl = opaque;
 
-    if (reg == fdctrl->io_base + 0x02)
+    switch (reg & 0x07) {
+    case 0x02:
 	fdctrl_write_dor(fdctrl, value);
-    else if (reg == fdctrl->io_base + 0x03)
+	break;
+    case 0x03:
         fdctrl_write_tape(fdctrl, value);
-    else if (reg == fdctrl->io_base + 0x04)
+	break;
+    case 0x04:
         fdctrl_write_rate(fdctrl, value);
-    else if (reg == fdctrl->io_base + 0x05)
+	break;
+    case 0x05:
         fdctrl_write_data(fdctrl, value);
+	break;
+    default:
+	break;
+    }
 }
 
 static void fd_change_cb (void *opaque)
@@ -581,7 +456,6 @@ static void fd_change_cb (void *opaque)
     fdrive_t *drv = opaque;
 
     FLOPPY_DPRINTF("disk change\n");
-    /* TODO: use command-line parameters to force geometry */
     fd_revalidate(drv);
 #if 0
     fd_recalibrate(drv);
@@ -606,7 +480,7 @@ fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
     fdctrl->irq_lvl = irq_lvl;
     fdctrl->dma_chann = dma_chann;
     fdctrl->io_base = io_base;
-    fdctrl->config = 0x40; /* Implicit seek, polling & FIFO enabled */
+    fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */
     if (fdctrl->dma_chann != -1) {
         fdctrl->dma_en = 1;
         DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
@@ -634,9 +508,10 @@ fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
         register_ioport_write(io_base + 0x01, 5, 1, &fdctrl_write, fdctrl);
         register_ioport_write(io_base + 0x07, 1, 1, &fdctrl_write, fdctrl);
     }
-    for (i = 0; i < MAX_FD; i++) {
+    for (i = 0; i < 2; i++) {
         fd_revalidate(&fdctrl->drives[i]);
     }
+
     return fdctrl;
 }
 
diff --git a/hw/i8259.c b/hw/i8259.c
index 8fabaf7..adc9ced 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -174,7 +174,7 @@ static inline void pic_intack(PicState *s, int irq)
     s->irr &= ~(1 << irq);
 }
 
-int cpu_x86_get_pic_interrupt(CPUState *env)
+int cpu_get_pic_interrupt(CPUState *env)
 {
     int irq, irq2, intno;
 
diff --git a/hw/m48t59.c b/hw/m48t59.c
new file mode 100644
index 0000000..fbee94f
--- /dev/null
+++ b/hw/m48t59.c
@@ -0,0 +1,486 @@
+/*
+ * QEMU M48T59 NVRAM emulation for PPC PREP platform
+ * 
+ * Copyright (c) 2003-2004 Jocelyn Mayer
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <stdio.h> /* needed by vl.h */
+#include <stdint.h>
+#include <string.h>
+#include <time.h>
+
+#include "vl.h"
+
+//#define NVRAM_DEBUG
+
+#if defined(NVRAM_DEBUG)
+#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
+#else
+#define NVRAM_PRINTF(fmt, args...) do { } while (0)
+#endif
+
+typedef struct m48t59_t {
+    /* Hardware parameters */
+    int      IRQ;
+    uint32_t io_base;
+    uint16_t size;
+    /* RTC management */
+    time_t   time_offset;
+    time_t   stop_time;
+    /* Alarm & watchdog */
+    time_t   alarm;
+    struct QEMUTimer *alrm_timer;
+    struct QEMUTimer *wd_timer;
+    /* NVRAM storage */
+    uint16_t addr;
+    uint8_t *buffer;
+} m48t59_t;
+
+static m48t59_t *NVRAMs;
+static int nb_NVRAMs;
+
+/* Fake timer functions */
+/* Generic helpers for BCD */
+static inline uint8_t toBCD (uint8_t value)
+{
+    return (((value / 10) % 10) << 4) | (value % 10);
+}
+
+static inline uint8_t fromBCD (uint8_t BCD)
+{
+    return ((BCD >> 4) * 10) + (BCD & 0x0F);
+}
+
+/* RTC management helpers */
+static void get_time (m48t59_t *NVRAM, struct tm *tm)
+{
+    time_t t;
+
+    t = time(NULL) + NVRAM->time_offset;
+    localtime_r(&t, tm);
+}
+
+static void set_time (m48t59_t *NVRAM, struct tm *tm)
+{
+    time_t now, new_time;
+    
+    new_time = mktime(tm);
+    now = time(NULL);
+    NVRAM->time_offset = new_time - now;
+}
+
+/* Alarm management */
+static void alarm_cb (void *opaque)
+{
+    struct tm tm, tm_now;
+    uint64_t next_time;
+    m48t59_t *NVRAM = opaque;
+
+    pic_set_irq(NVRAM->IRQ, 1);
+    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && 
+	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
+	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
+	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
+	/* Repeat once a month */
+	get_time(NVRAM, &tm_now);
+	memcpy(&tm, &tm_now, sizeof(struct tm));
+	tm.tm_mon++;
+	if (tm.tm_mon == 13) {
+	    tm.tm_mon = 1;
+	    tm.tm_year++;
+	}
+	next_time = mktime(&tm);
+    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
+	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
+	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
+	/* Repeat once a day */
+	next_time = 24 * 60 * 60 + mktime(&tm_now);
+    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
+	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
+	/* Repeat once an hour */
+	next_time = 60 * 60 + mktime(&tm_now);
+    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
+	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
+	/* Repeat once a minute */
+	next_time = 60 + mktime(&tm_now);
+    } else {
+	/* Repeat once a second */
+	next_time = 1 + mktime(&tm_now);
+    }
+    qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
+    pic_set_irq(NVRAM->IRQ, 0);
+}
+
+
+static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
+{
+    localtime_r(&NVRAM->alarm, tm);
+}
+
+static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
+{
+    NVRAM->alarm = mktime(tm);
+    if (NVRAM->alrm_timer != NULL) {
+        qemu_del_timer(NVRAM->alrm_timer);
+	NVRAM->alrm_timer = NULL;
+    }
+    if (NVRAM->alarm - time(NULL) > 0)
+	qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
+}
+
+/* Watchdog management */
+static void watchdog_cb (void *opaque)
+{
+    m48t59_t *NVRAM = opaque;
+
+    NVRAM->buffer[0x1FF0] |= 0x80;
+    if (NVRAM->buffer[0x1FF7] & 0x80) {
+	NVRAM->buffer[0x1FF7] = 0x00;
+	NVRAM->buffer[0x1FFC] &= ~0x40;
+	//	reset_CPU();
+    } else {
+	pic_set_irq(NVRAM->IRQ, 1);
+	pic_set_irq(NVRAM->IRQ, 0);
+    }
+}
+
+static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
+{
+    uint64_t interval; /* in 1/16 seconds */
+
+    if (NVRAM->wd_timer != NULL) {
+        qemu_del_timer(NVRAM->wd_timer);
+	NVRAM->wd_timer = NULL;
+    }
+    NVRAM->buffer[0x1FF0] &= ~0x80;
+    if (value != 0) {
+	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
+	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
+		       ((interval * 1000) >> 4));
+    }
+}
+
+/* Direct access to NVRAM */
+void m48t59_write (void *opaque, uint32_t val)
+{
+    m48t59_t *NVRAM = opaque;
+    struct tm tm;
+    int tmp;
+
+    if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
+	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
+    switch (NVRAM->addr) {
+    case 0x1FF0:
+        /* flags register : read-only */
+        break;
+    case 0x1FF1:
+        /* unused */
+        break;
+    case 0x1FF2:
+        /* alarm seconds */
+	tmp = fromBCD(val & 0x7F);
+	if (tmp >= 0 && tmp <= 59) {
+	    get_alarm(NVRAM, &tm);
+	    tm.tm_sec = tmp;
+	    NVRAM->buffer[0x1FF2] = val;
+	    set_alarm(NVRAM, &tm);
+	}
+        break;
+    case 0x1FF3:
+        /* alarm minutes */
+	tmp = fromBCD(val & 0x7F);
+	if (tmp >= 0 && tmp <= 59) {
+	    get_alarm(NVRAM, &tm);
+	    tm.tm_min = tmp;
+	    NVRAM->buffer[0x1FF3] = val;
+	    set_alarm(NVRAM, &tm);
+	}
+        break;
+    case 0x1FF4:
+        /* alarm hours */
+	tmp = fromBCD(val & 0x3F);
+	if (tmp >= 0 && tmp <= 23) {
+	    get_alarm(NVRAM, &tm);
+	    tm.tm_hour = tmp;
+	    NVRAM->buffer[0x1FF4] = val;
+	    set_alarm(NVRAM, &tm);
+	}
+        break;
+    case 0x1FF5:
+        /* alarm date */
+	tmp = fromBCD(val & 0x1F);
+	if (tmp != 0) {
+	    get_alarm(NVRAM, &tm);
+	    tm.tm_mday = tmp;
+	    NVRAM->buffer[0x1FF5] = val;
+	    set_alarm(NVRAM, &tm);
+	}
+        break;
+    case 0x1FF6:
+        /* interrupts */
+	NVRAM->buffer[0x1FF6] = val;
+        break;
+    case 0x1FF7:
+        /* watchdog */
+	NVRAM->buffer[0x1FF7] = val;
+	set_up_watchdog(NVRAM, val);
+        break;
+    case 0x1FF8:
+        /* control */
+	NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
+        break;
+    case 0x1FF9:
+        /* seconds (BCD) */
+	tmp = fromBCD(val & 0x7F);
+	if (tmp >= 0 && tmp <= 59) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_sec = tmp;
+	    set_time(NVRAM, &tm);
+	}
+	if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
+	    if (val & 0x80) {
+		NVRAM->stop_time = time(NULL);
+	    } else {
+		NVRAM->time_offset += NVRAM->stop_time - time(NULL);
+		NVRAM->stop_time = 0;
+	    }
+	}
+	NVRAM->buffer[0x1FF9] = val & 0x80;
+        break;
+    case 0x1FFA:
+        /* minutes (BCD) */
+	tmp = fromBCD(val & 0x7F);
+	if (tmp >= 0 && tmp <= 59) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_min = tmp;
+	    set_time(NVRAM, &tm);
+	}
+        break;
+    case 0x1FFB:
+        /* hours (BCD) */
+	tmp = fromBCD(val & 0x3F);
+	if (tmp >= 0 && tmp <= 23) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_hour = tmp;
+	    set_time(NVRAM, &tm);
+	}
+        break;
+    case 0x1FFC:
+        /* day of the week / century */
+	tmp = fromBCD(val & 0x07);
+	get_time(NVRAM, &tm);
+	tm.tm_wday = tmp;
+	set_time(NVRAM, &tm);
+        NVRAM->buffer[0x1FFC] = val & 0x40;
+        break;
+    case 0x1FFD:
+        /* date */
+	tmp = fromBCD(val & 0x1F);
+	if (tmp != 0) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_mday = tmp;
+	    set_time(NVRAM, &tm);
+	}
+        break;
+    case 0x1FFE:
+        /* month */
+	tmp = fromBCD(val & 0x1F);
+	if (tmp >= 1 && tmp <= 12) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_mon = tmp - 1;
+	    set_time(NVRAM, &tm);
+	}
+        break;
+    case 0x1FFF:
+        /* year */
+	tmp = fromBCD(val);
+	if (tmp >= 0 && tmp <= 99) {
+	    get_time(NVRAM, &tm);
+	    tm.tm_year = fromBCD(val);
+	    set_time(NVRAM, &tm);
+	}
+        break;
+    default:
+        if (NVRAM->addr < 0x1FF0 ||
+	    (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
+            NVRAM->buffer[NVRAM->addr] = val & 0xFF;
+	}
+        break;
+    }
+}
+
+uint32_t m48t59_read (void *opaque)
+{
+    m48t59_t *NVRAM = opaque;
+    struct tm tm;
+    uint32_t retval = 0xFF;
+
+    switch (NVRAM->addr) {
+    case 0x1FF0:
+        /* flags register */
+	goto do_read;
+    case 0x1FF1:
+        /* unused */
+	retval = 0;
+        break;
+    case 0x1FF2:
+        /* alarm seconds */
+	goto do_read;
+    case 0x1FF3:
+        /* alarm minutes */
+	goto do_read;
+    case 0x1FF4:
+        /* alarm hours */
+	goto do_read;
+    case 0x1FF5:
+        /* alarm date */
+	goto do_read;
+    case 0x1FF6:
+        /* interrupts */
+	goto do_read;
+    case 0x1FF7:
+	/* A read resets the watchdog */
+	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
+	goto do_read;
+    case 0x1FF8:
+        /* control */
+	goto do_read;
+    case 0x1FF9:
+        /* seconds (BCD) */
+        get_time(NVRAM, &tm);
+        retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
+        break;
+    case 0x1FFA:
+        /* minutes (BCD) */
+        get_time(NVRAM, &tm);
+        retval = toBCD(tm.tm_min);
+        break;
+    case 0x1FFB:
+        /* hours (BCD) */
+        get_time(NVRAM, &tm);
+        retval = toBCD(tm.tm_hour);
+        break;
+    case 0x1FFC:
+        /* day of the week / century */
+        get_time(NVRAM, &tm);
+        retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
+        break;
+    case 0x1FFD:
+        /* date */
+        get_time(NVRAM, &tm);
+        retval = toBCD(tm.tm_mday);
+        break;
+    case 0x1FFE:
+        /* month */
+        get_time(NVRAM, &tm);
+        retval = toBCD(tm.tm_mon + 1);
+        break;
+    case 0x1FFF:
+        /* year */
+        get_time(NVRAM, &tm);
+        retval = toBCD(tm.tm_year);
+        break;
+    default:
+        if (NVRAM->addr < 0x1FF0 ||
+	    (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
+	do_read:
+            retval = NVRAM->buffer[NVRAM->addr];
+	}
+        break;
+    }
+    if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
+	NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
+
+    return retval;
+}
+
+void m48t59_set_addr (void *opaque, uint32_t addr)
+{
+    m48t59_t *NVRAM = opaque;
+
+    NVRAM->addr = addr;
+}
+
+/* IO access to NVRAM */
+static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
+{
+    m48t59_t *NVRAM = opaque;
+
+    addr -= NVRAM->io_base;
+    switch (addr) {
+    case 0:
+        NVRAM->addr &= ~0x00FF;
+        NVRAM->addr |= val;
+        break;
+    case 1:
+        NVRAM->addr &= ~0xFF00;
+        NVRAM->addr |= val << 8;
+        break;
+    case 3:
+        m48t59_write(NVRAM, val);
+        NVRAM->addr = 0x0000;
+        break;
+    default:
+        break;
+    }
+}
+
+static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
+{
+    m48t59_t *NVRAM = opaque;
+
+    if (addr == NVRAM->io_base + 3)
+        return m48t59_read(NVRAM);
+
+    return 0xFF;
+}
+
+/* Initialisation routine */
+void *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
+{
+    m48t59_t *tmp;
+
+    tmp = realloc(NVRAMs, (nb_NVRAMs + 1) * sizeof(m48t59_t));
+    if (tmp == NULL)
+	return NULL;
+    NVRAMs = tmp;
+    tmp[nb_NVRAMs].buffer = malloc(size);
+    if (tmp[nb_NVRAMs].buffer == NULL)
+	return NULL;
+    memset(tmp[nb_NVRAMs].buffer, 0, size);
+    tmp[nb_NVRAMs].IRQ = IRQ;
+    tmp[nb_NVRAMs].size = size;
+    tmp[nb_NVRAMs].io_base = io_base;
+    tmp[nb_NVRAMs].addr = 0;
+    register_ioport_read(io_base, 0x04, 1, NVRAM_readb, &NVRAMs[nb_NVRAMs]);
+    register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, &NVRAMs[nb_NVRAMs]);
+    tmp[nb_NVRAMs].alrm_timer = qemu_new_timer(vm_clock, &alarm_cb,
+					       &tmp[nb_NVRAMs]);
+    tmp[nb_NVRAMs].wd_timer = qemu_new_timer(vm_clock, &watchdog_cb,
+					     &tmp[nb_NVRAMs]);
+    return &NVRAMs[nb_NVRAMs++];
+}
diff --git a/hw/m48t59.h b/hw/m48t59.h
new file mode 100644
index 0000000..f73846d
--- /dev/null
+++ b/hw/m48t59.h
@@ -0,0 +1,9 @@
+#if !defined (__M48T59_H__)
+#define __M48T59_H__
+
+void m48t59_write (void *opaque, uint32_t val);
+uint32_t m48t59_read (void *opaque);
+void m48t59_set_addr (void *opaque, uint32_t addr);
+void *m48t59_init (int IRQ, uint32_t io_base, uint16_t size);
+
+#endif /* !defined (__M48T59_H__) */
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 63edf03..e9ad6f9 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -146,6 +146,10 @@ static void ne2000_update_irq(NE2000State *s)
 {
     int isr;
     isr = s->isr & s->imr;
+#if defined(DEBUG_NE2000)
+    printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
+	   s->irq, isr ? 1 : 0, s->isr, s->imr);
+#endif
     if (isr)
         pic_set_irq(s->irq, 1);
     else
diff --git a/hw/ppc.c b/hw/ppc.c
new file mode 100644
index 0000000..cd485bc
--- /dev/null
+++ b/hw/ppc.c
@@ -0,0 +1,42 @@
+/*
+ * QEMU generic PPC hardware System Emulator
+ * 
+ * Copyright (c) 2003-2004 Jocelyn Mayer
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include "vl.h"
+
+void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
+		    DisplayState *ds, const char **fd_filename, int snapshot,
+		    const char *kernel_filename, const char *kernel_cmdline,
+		    const char *initrd_filename);
+
+void ppc_init (int ram_size, int vga_ram_size, int boot_device,
+	       DisplayState *ds, const char **fd_filename, int snapshot,
+	       const char *kernel_filename, const char *kernel_cmdline,
+	       const char *initrd_filename)
+{
+    /* For now, only PREP is supported */
+    return ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
+			 snapshot, kernel_filename, kernel_cmdline,
+			 initrd_filename);
+}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
new file mode 100644
index 0000000..32b2ce8
--- /dev/null
+++ b/hw/ppc_prep.c
@@ -0,0 +1,1007 @@
+/*
+ * QEMU PPC PREP hardware System Emulator
+ * 
+ * Copyright (c) 2003-2004 Jocelyn Mayer
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include <getopt.h>
+#include <inttypes.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include <termios.h>
+#include <sys/poll.h>
+#include <errno.h>
+#include <sys/wait.h>
+#include <netinet/in.h>
+
+#include "cpu.h"
+#include "vl.h"
+#include "m48t59.h"
+
+//#define HARD_DEBUG_PPC_IO
+//#define DEBUG_PPC_IO
+
+extern int loglevel;
+extern FILE *logfile;
+
+#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
+#define DEBUG_PPC_IO
+#endif
+
+#if defined (HARD_DEBUG_PPC_IO)
+#define PPC_IO_DPRINTF(fmt, args...)                     \
+do {                                                     \
+    if (loglevel > 0) {                                  \
+        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
+    } else {                                             \
+        printf("%s : " fmt, __func__ , ##args);          \
+    }                                                    \
+} while (0)
+#elif defined (DEBUG_PPC_IO)
+#define PPC_IO_DPRINTF(fmt, args...)                     \
+do {                                                     \
+    if (loglevel > 0) {                                  \
+        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
+    }                                                    \
+} while (0)
+#else
+#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
+#endif
+
+#define BIOS_FILENAME "ppc_rom.bin"
+#define LINUX_BOOT_FILENAME "linux_boot.bin"
+
+#define KERNEL_LOAD_ADDR    0x00000000
+#define KERNEL_STACK_ADDR   0x00400000
+#define INITRD_LOAD_ADDR    0x00800000
+
+int load_kernel(const char *filename, uint8_t *addr, 
+                uint8_t *real_addr)
+{
+    int fd, size;
+    int setup_sects;
+
+    fd = open(filename, O_RDONLY);
+    if (fd < 0)
+        return -1;
+
+    /* load 16 bit code */
+    if (read(fd, real_addr, 512) != 512)
+        goto fail;
+    setup_sects = real_addr[0x1F1];
+    if (!setup_sects)
+        setup_sects = 4;
+    if (read(fd, real_addr + 512, setup_sects * 512) != 
+        setup_sects * 512)
+        goto fail;
+    
+    /* load 32 bit code */
+    size = read(fd, addr, 16 * 1024 * 1024);
+    if (size < 0)
+        goto fail;
+    close(fd);
+    return size;
+ fail:
+    close(fd);
+    return -1;
+}
+
+static const int ide_iobase[2] = { 0x1f0, 0x170 };
+static const int ide_iobase2[2] = { 0x3f6, 0x376 };
+static const int ide_irq[2] = { 13, 13 };
+
+#define NE2000_NB_MAX 6
+
+static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
+static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
+
+/* IO ports emulation */
+#define PPC_IO_BASE 0x80000000
+
+static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
+{
+    /* Don't polute serial port output */
+#if 0
+    if ((addr < 0x800003F0 || addr > 0x80000400) &&
+        (addr < 0x80000074 || addr > 0x80000077) &&
+        (addr < 0x80000020 || addr > 0x80000021) &&
+        (addr < 0x800000a0 || addr > 0x800000a1) &&
+        (addr < 0x800001f0 || addr > 0x800001f7) &&
+        (addr < 0x80000170 || addr > 0x80000177)) 
+#endif
+    {
+        PPC_IO_DPRINTF("0x%08x => 0x%02x\n", addr - PPC_IO_BASE, value);
+    }
+    cpu_outb(NULL, addr - PPC_IO_BASE, value);
+}
+
+static uint32_t PPC_io_readb (uint32_t addr)
+{
+    uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
+
+#if 0
+    if ((addr < 0x800003F0 || addr > 0x80000400) &&
+        (addr < 0x80000074 || addr > 0x80000077) &&
+        (addr < 0x80000020 || addr > 0x80000021) &&
+        (addr < 0x800000a0 || addr > 0x800000a1) &&
+        (addr < 0x800001f0 || addr > 0x800001f7) &&
+        (addr < 0x80000170 || addr > 0x80000177) &&
+        (addr < 0x8000060 || addr > 0x8000064))
+#endif
+    {
+        PPC_IO_DPRINTF("0x%08x <= 0x%02x\n", addr - PPC_IO_BASE, ret);
+    }
+
+    return ret;
+}
+
+static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
+{
+    if ((addr < 0x800001f0 || addr > 0x800001f7) &&
+        (addr < 0x80000170 || addr > 0x80000177)) {
+        PPC_IO_DPRINTF("0x%08x => 0x%04x\n", addr - PPC_IO_BASE, value);
+    }
+    cpu_outw(NULL, addr - PPC_IO_BASE, value);
+}
+
+static uint32_t PPC_io_readw (uint32_t addr)
+{
+    uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
+
+    if ((addr < 0x800001f0 || addr > 0x800001f7) &&
+        (addr < 0x80000170 || addr > 0x80000177)) {
+        PPC_IO_DPRINTF("0x%08x <= 0x%04x\n", addr - PPC_IO_BASE, ret);
+    }
+
+    return ret;
+}
+
+static void PPC_io_writel (uint32_t addr, uint32_t value, uint32_t vaddr)
+{
+    PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
+    cpu_outl(NULL, addr - PPC_IO_BASE, value);
+}
+
+static uint32_t PPC_io_readl (uint32_t addr)
+{
+    uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
+
+    PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, ret);
+
+    return ret;
+}
+
+static CPUWriteMemoryFunc *PPC_io_write[] = {
+    &PPC_io_writeb,
+    &PPC_io_writew,
+    &PPC_io_writel,
+};
+
+static CPUReadMemoryFunc *PPC_io_read[] = {
+    &PPC_io_readb,
+    &PPC_io_readw,
+    &PPC_io_readl,
+};
+
+uint32_t pic_intack_read(CPUState *env);
+
+/* Read-only register (?) */
+static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr)
+{
+    //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
+}
+
+static uint32_t _PPC_ioB_read (uint32_t addr)
+{
+    uint32_t retval = 0;
+
+    if (addr == 0xBFFFFFF0)
+        retval = pic_intack_read(NULL);
+       //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
+
+    return retval;
+}
+
+static CPUWriteMemoryFunc *PPC_ioB_write[] = {
+    &_PPC_ioB_write,
+    &_PPC_ioB_write,
+    &_PPC_ioB_write,
+};
+
+static CPUReadMemoryFunc *PPC_ioB_read[] = {
+    &_PPC_ioB_read,
+    &_PPC_ioB_read,
+    &_PPC_ioB_read,
+};
+
+#if 0
+static CPUWriteMemoryFunc *PPC_io3_write[] = {
+    &PPC_io3_writeb,
+    &PPC_io3_writew,
+    &PPC_io3_writel,
+};
+
+static CPUReadMemoryFunc *PPC_io3_read[] = {
+    &PPC_io3_readb,
+    &PPC_io3_readw,
+    &PPC_io3_readl,
+};
+#endif
+
+/* Fake super-io ports for PREP platform (Intel 82378ZB) */
+static uint8_t PREP_fake_io[2];
+static uint8_t NVRAM_lock;
+
+static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
+{
+    PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
+    PREP_fake_io[addr - 0x0398] = val;
+}
+
+static uint32_t PREP_io_read (void *opaque, uint32_t addr)
+{
+    PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, PREP_fake_io[addr - 0x0398]);
+    return PREP_fake_io[addr - 0x0398];
+}
+
+static uint8_t syscontrol;
+
+static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
+{
+    PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
+    switch (addr) {
+    case 0x0092:
+        /* Special port 92 */
+        /* Check soft reset asked */
+        if (val & 0x80) {
+            printf("Soft reset asked... Stop emulation\n");
+            abort();
+        }
+        /* Check LE mode */
+        if (val & 0x40) {
+            printf("Little Endian mode isn't supported (yet ?)\n");
+            abort();
+        }
+        break;
+    case 0x0808:
+        /* Hardfile light register: don't care */
+        break;
+    case 0x0810:
+        /* Password protect 1 register */
+        NVRAM_lock ^= 0x01;
+        break;
+    case 0x0812:
+        /* Password protect 2 register */
+        NVRAM_lock ^= 0x02;
+        break;
+    case 0x0814:
+        /* L2 invalidate register: don't care */
+        break;
+    case 0x081C:
+        /* system control register */
+        syscontrol = val;
+        break;
+    case 0x0850:
+        /* I/O map type register */
+        if (val & 0x80) {
+            printf("No support for non-continuous I/O map mode\n");
+            abort();
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
+{
+    uint32_t retval = 0xFF;
+
+    switch (addr) {
+    case 0x0092:
+        /* Special port 92 */
+        retval = 0x40;
+        break;
+    case 0x080C:
+        /* Equipment present register:
+         *  no L2 cache
+         *  no upgrade processor
+         *  no cards in PCI slots
+         *  SCSI fuse is bad
+         */
+        retval = 0xFC;
+        break;
+    case 0x0818:
+        /* Keylock */
+        retval = 0x00;
+        break;
+    case 0x081C:
+        /* system control register
+         * 7 - 6 / 1 - 0: L2 cache enable
+         */
+        retval = syscontrol;
+        break;
+    case 0x0823:
+        /* */
+        retval = 0x03; /* no L2 cache */
+        break;
+    case 0x0850:
+        /* I/O map type register */
+        retval = 0x00;
+        break;
+    default:
+        break;
+    }
+    PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, retval);
+
+    return retval;
+}
+
+#define NVRAM_SIZE        0x2000
+#define NVRAM_END         0x1FF0
+#define NVRAM_OSAREA_SIZE 512
+#define NVRAM_CONFSIZE    1024
+
+static inline void NVRAM_set_byte (void *opaque, uint32_t addr, uint8_t value)
+{
+    m48t59_set_addr(opaque, addr);
+    m48t59_write(opaque, value);
+}
+
+static inline uint8_t NVRAM_get_byte (void *opaque, uint32_t addr)
+{
+    m48t59_set_addr(opaque, addr);
+    return m48t59_read(opaque);
+}
+
+static inline void NVRAM_set_word (void *opaque, uint32_t addr, uint16_t value)
+{
+    m48t59_set_addr(opaque, addr);
+    m48t59_write(opaque, value >> 8);
+    m48t59_set_addr(opaque, addr + 1);
+    m48t59_write(opaque, value & 0xFF);
+}
+
+static inline uint16_t NVRAM_get_word (void *opaque, uint32_t addr)
+{
+    uint16_t tmp;
+
+    m48t59_set_addr(opaque, addr);
+    tmp = m48t59_read(opaque) << 8;
+    m48t59_set_addr(opaque, addr + 1);
+    tmp |= m48t59_read(opaque);
+
+    return tmp;
+}
+
+static inline void NVRAM_set_lword (void *opaque, uint32_t addr,
+				    uint32_t value)
+{
+    m48t59_set_addr(opaque, addr);
+    m48t59_write(opaque, value >> 24);
+    m48t59_set_addr(opaque, addr + 1);
+    m48t59_write(opaque, (value >> 16) & 0xFF);
+    m48t59_set_addr(opaque, addr + 2);
+    m48t59_write(opaque, (value >> 8) & 0xFF);
+    m48t59_set_addr(opaque, addr + 3);
+    m48t59_write(opaque, value & 0xFF);
+}
+
+static inline uint32_t NVRAM_get_lword (void *opaque, uint32_t addr)
+{
+    uint32_t tmp;
+
+    m48t59_set_addr(opaque, addr);
+    tmp = m48t59_read(opaque) << 24;
+    m48t59_set_addr(opaque, addr + 1);
+    tmp |= m48t59_read(opaque) << 16;
+    m48t59_set_addr(opaque, addr + 2);
+    tmp |= m48t59_read(opaque) << 8;
+    m48t59_set_addr(opaque, addr + 3);
+    tmp |= m48t59_read(opaque);
+
+    return tmp;
+}
+
+static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
+{
+    uint16_t tmp;
+    uint16_t pd, pd1, pd2;
+
+    tmp = prev >> 8;
+    pd = prev ^ value;
+    pd1 = pd & 0x000F;
+    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
+    tmp ^= (pd1 << 3) | (pd1 << 8);
+    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
+
+    return tmp;
+}
+
+static void NVRAM_set_crc (void *opaque, uint32_t addr,
+			   uint32_t start, uint32_t count)
+{
+    uint32_t i;
+    uint16_t crc = 0xFFFF;
+    int odd = 0;
+
+    if (count & 1)
+	odd = 1;
+    count &= ~1;
+    for (i = 0; i != count; i++) {
+	crc = NVRAM_crc_update(crc, NVRAM_get_word(opaque, start + i));
+    }
+    if (odd) {
+	crc = NVRAM_crc_update(crc, NVRAM_get_byte(opaque, start + i) << 8);
+    }
+    NVRAM_set_word(opaque, addr, crc);
+}
+
+static void prep_NVRAM_init (void)
+{
+    void *opaque;
+
+    opaque = m48t59_init(8, 0x0074, NVRAM_SIZE);
+    /* NVRAM header */
+    /* 0x00: NVRAM size in kB */
+    NVRAM_set_word(opaque, 0x00, NVRAM_SIZE >> 10);
+    /* 0x02: NVRAM version */
+    NVRAM_set_byte(opaque, 0x02, 0x01);
+    /* 0x03: NVRAM revision */
+    NVRAM_set_byte(opaque, 0x03, 0x01);
+    /* 0x08: last OS */
+    NVRAM_set_byte(opaque, 0x08, 0x00); /* Unknown */
+    /* 0x09: endian */
+    NVRAM_set_byte(opaque, 0x09, 'B');  /* Big-endian */
+    /* 0x0A: OSArea usage */
+    NVRAM_set_byte(opaque, 0x0A, 0x00); /* Empty */
+    /* 0x0B: PM mode */
+    NVRAM_set_byte(opaque, 0x0B, 0x00); /* Normal */
+    /* Restart block description record */
+    /* 0x0C: restart block version */
+    NVRAM_set_word(opaque, 0x0C, 0x01);
+    /* 0x0E: restart block revision */
+    NVRAM_set_word(opaque, 0x0E, 0x01);
+    /* 0x20: restart address */
+    NVRAM_set_lword(opaque, 0x20, 0x00);
+    /* 0x24: save area address */
+    NVRAM_set_lword(opaque, 0x24, 0x00);
+    /* 0x28: save area length */
+    NVRAM_set_lword(opaque, 0x28, 0x00);
+    /* 0x1C: checksum of restart block */
+    NVRAM_set_crc(opaque, 0x1C, 0x0C, 32);
+
+    /* Security section */
+    /* Set all to zero */
+    /* 0xC4: pointer to global environment area */
+    NVRAM_set_lword(opaque, 0xC4, 0x0100);
+    /* 0xC8: size of global environment area */
+    NVRAM_set_lword(opaque, 0xC8,
+		    NVRAM_END - NVRAM_OSAREA_SIZE - NVRAM_CONFSIZE - 0x0100);
+    /* 0xD4: pointer to configuration area */
+    NVRAM_set_lword(opaque, 0xD4, NVRAM_END - NVRAM_CONFSIZE);
+    /* 0xD8: size of configuration area */
+    NVRAM_set_lword(opaque, 0xD8, NVRAM_CONFSIZE);
+    /* 0xE8: pointer to OS specific area */
+    NVRAM_set_lword(opaque, 0xE8,
+		    NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
+    /* 0xD8: size of OS specific area */
+    NVRAM_set_lword(opaque, 0xEC, NVRAM_OSAREA_SIZE);
+
+    /* Configuration area */
+    /* RTC init */
+    //    NVRAM_set_lword(opaque, 0x1FFC, 0x50);
+
+    /* 0x04: checksum 0 => OS area   */
+    NVRAM_set_crc(opaque, 0x04, 0x00,
+		  NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
+    /* 0x06: checksum of config area */
+    NVRAM_set_crc(opaque, 0x06, NVRAM_END - NVRAM_CONFSIZE, NVRAM_CONFSIZE);
+}
+
+int load_initrd (const char *filename, uint8_t *addr)
+{
+    int fd, size;
+
+    printf("Load initrd\n");
+    fd = open(filename, O_RDONLY);
+    if (fd < 0)
+        return -1;
+    size = read(fd, addr, 16 * 1024 * 1024);
+    if (size < 0)
+        goto fail;
+    close(fd);
+    printf("Load initrd: %d\n", size);
+    return size;
+ fail:
+    close(fd);
+    printf("Load initrd failed\n");
+    return -1;
+}
+
+/* Quick hack for PPC memory infos... */
+static void put_long (void *addr, uint32_t l)
+{
+    char *pos = addr;
+    pos[0] = (l >> 24) & 0xFF;
+    pos[1] = (l >> 16) & 0xFF;
+    pos[2] = (l >> 8) & 0xFF;
+    pos[3] = l & 0xFF;
+}
+
+/* bootloader infos are in the form:
+ * uint32_t TAG
+ * uint32_t TAG_size (from TAG to next TAG).
+ * data
+ * ....
+ */
+#if !defined (USE_OPEN_FIRMWARE)
+static void *set_bootinfo_tag (void *addr, uint32_t tag, uint32_t size,
+                               void *data)
+{
+    char *pos = addr;
+
+    put_long(pos, tag);
+    pos += 4;
+    put_long(pos, size + 8);
+    pos += 4;
+    memcpy(pos, data, size);
+    pos += size;
+
+    return pos;
+}
+#endif
+
+typedef struct boot_dev_t {
+    const unsigned char *name;
+    int major;
+    int minor;
+} boot_dev_t;
+
+static boot_dev_t boot_devs[] = 
+{
+    { "/dev/fd0", 2, 0, },
+    { "/dev/fd1", 2, 1, },
+    { "/dev/hda", 3, 1, },
+//    { "/dev/ide/host0/bus0/target0/lun0/part1", 3, 1, },
+//    { "/dev/hdc", 22, 0, },
+    { "/dev/hdc", 22, 1, },
+    { "/dev/ram0 init=/linuxrc", 1, 0, },
+};
+
+/* BATU:
+ * BEPI  : bloc virtual address
+ * BL    : area size bits (128 kB is 0, 256 1, 512 3, ...
+ * Vs/Vp
+ * BATL:
+ * BPRN  : bloc real address align on 4MB boundary
+ * WIMG  : cache access mode : not used
+ * PP    : protection bits
+ */
+static void setup_BAT (CPUPPCState *env, int BAT,
+                       uint32_t virtual, uint32_t physical,
+                       uint32_t size, int Vs, int Vp, int PP)
+{
+    uint32_t sz_bits, tmp_sz, align, tmp;
+    
+    sz_bits = 0;
+    align = 131072;
+    for (tmp_sz = size / 131072; tmp_sz != 1; tmp_sz = tmp_sz >> 1) {
+        sz_bits = (sz_bits << 1) + 1;
+        align = align << 1;
+    }
+    tmp = virtual & ~(align - 1);  /* Align virtual area start */
+    tmp |= sz_bits << 2;           /* Fix BAT size             */
+    tmp |= Vs << 1;                /* Supervisor access        */
+    tmp |= Vp;                     /* User access              */
+    env->DBAT[0][BAT] = tmp;
+    env->IBAT[0][BAT] = tmp;
+    tmp = physical & ~(align - 1); /* Align physical area start */
+    tmp |= 0;                      /* Don't care about WIMG     */
+    tmp |= PP;                     /* Protection                */
+    env->DBAT[1][BAT] = tmp;
+    env->IBAT[1][BAT] = tmp;
+    printf("Set BATU0 to 0x%08x BATL0 to 0x%08x\n",
+           env->DBAT[0][BAT], env->DBAT[1][BAT]);
+}
+
+static void VGA_printf (uint8_t *s)
+{
+    uint16_t *arg_ptr;
+    unsigned int format_width, i;
+    int in_format;
+    uint16_t arg, digit, nibble;
+    uint8_t c;
+
+    arg_ptr = (uint16_t *)((void *)&s);
+    in_format = 0;
+    format_width = 0;
+    while ((c = *s) != '\0') {
+        if (c == '%') {
+            in_format = 1;
+            format_width = 0;
+        } else if (in_format) {
+            if ((c >= '0') && (c <= '9')) {
+                format_width = (format_width * 10) + (c - '0');
+            } else if (c == 'x') {
+                arg_ptr++; // increment to next arg
+                arg = *arg_ptr;
+                if (format_width == 0)
+                    format_width = 4;
+                digit = format_width - 1;
+                for (i = 0; i < format_width; i++) {
+                    nibble = (arg >> (4 * digit)) & 0x000f;
+                    if (nibble <= 9)
+                        PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0', 0);
+                    else
+                        PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A', 0);
+                    digit--;
+                }
+                in_format = 0;
+            }
+            //else if (c == 'd') {
+            //  in_format = 0;
+            //  }
+        } else {
+            PPC_io_writeb(PPC_IO_BASE + 0x500, c, 0);
+        }
+        s++;
+    }
+}
+
+static void VGA_init (void)
+{
+    /* Basic VGA init, inspired by plex86 VGAbios */
+    printf("Init VGA...\n");
+#if 1
+    /* switch to color mode and enable CPU access 480 lines */
+    PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3, 0);
+    /* more than 64k 3C4/04 */
+    PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04, 0);
+    PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02, 0);
+#endif
+    VGA_printf("PPC VGA BIOS...\n");
+}
+
+extern CPUPPCState *global_env;
+
+void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
+                  uint32_t kernel_addr, uint32_t kernel_size,
+                  uint32_t stack_addr, int boot_device,
+		  const unsigned char *initrd_file)
+{
+    CPUPPCState *env = global_env;
+    char *p;
+#if !defined (USE_OPEN_FIRMWARE)
+    char *tmp;
+    uint32_t tmpi[2];
+#endif
+
+    printf("RAM size: %u 0x%08x (%u)\n", mem_size, mem_size, mem_size >> 20);
+#if defined (USE_OPEN_FIRMWARE)
+    setup_memory(env, mem_size);
+#endif
+
+    /* Fake bootloader */
+    {
+#if 1
+        uint32_t offset = 
+            *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
+#else
+        uint32_t offset = 12;
+#endif
+        env->nip = kernel_addr + offset;
+        printf("Start address: 0x%08x\n", env->nip);
+    }
+    /* Set up msr according to PREP specification */
+    msr_ee = 0;
+    msr_fp = 1;
+    msr_pr = 0; /* Start in supervisor mode */
+    msr_me = 1;
+    msr_fe0 = msr_fe1 = 0;
+    msr_ip = 0;
+    msr_ir = msr_dr = 1;
+//    msr_sf = 0;
+    msr_le = msr_ile = 0;
+    env->gpr[1] = stack_addr; /* Let's have a stack */
+    env->gpr[2] = 0;
+    env->gpr[8] = kernel_addr;
+    /* There is a bug in  2.4 kernels:
+     * if a decrementer exception is pending when it enables msr_ee,
+     * it's not ready to handle it...
+     */
+    env->decr = 0xFFFFFFFF;
+    p = (void *)(phys_ram_base + kernel_addr);
+#if !defined (USE_OPEN_FIRMWARE)
+    /* Let's register the whole memory available only in supervisor mode */
+    setup_BAT(env, 0, 0x00000000, 0x00000000, mem_size, 1, 0, 2);
+    /* Avoid open firmware init call (to get a console)
+     * This will make the kernel think we are a PREP machine...
+     */
+    put_long(p, 0xdeadc0de);
+    /* Build a real stack room */
+    p = (void *)(phys_ram_base + stack_addr);
+    put_long(p, stack_addr);
+    p -= 32;
+    env->gpr[1] -= 32;
+    /* Pretend there are no residual data */
+    env->gpr[3] = 0;
+    if (initrd_file != NULL) {
+        int size;
+        env->gpr[4] = (kernel_addr + kernel_size + 4095) & ~4095;
+        size = load_initrd(initrd_file,
+                           (void *)((uint32_t)phys_ram_base + env->gpr[4]));
+        if (size < 0) {
+            /* No initrd */
+            env->gpr[4] = env->gpr[5] = 0;
+        } else {
+            env->gpr[5] = size;
+            boot_device = 'e';
+        }
+        printf("Initrd loaded at 0x%08x (%d) (0x%08x 0x%08x)\n",
+	       env->gpr[4], env->gpr[5], kernel_addr, kernel_size);
+    } else {
+	env->gpr[4] = env->gpr[5] = 0;
+    }
+    /* We have to put bootinfos after the BSS
+     * The BSS starts after the kernel end.
+     */
+#if 0
+    p = (void *)(((uint32_t)phys_ram_base + kernel_addr +
+                  kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1));
+#else
+    p = (void *)((uint32_t)phys_ram_base + kernel_addr + 0x400000);
+#endif
+    if (loglevel > 0) {
+        fprintf(logfile, "bootinfos: %p 0x%08x\n",
+                p, (uint32_t)p - (uint32_t)phys_ram_base);
+    } else {
+        printf("bootinfos: %p 0x%08x\n",
+               p, (uint32_t)p - (uint32_t)phys_ram_base);
+    }
+    /* Command line: let's put it after bootinfos */
+#if 0
+    sprintf(p + 0x1000, "console=ttyS0,9600 root=%02x%02x mem=%dM",
+            boot_devs[boot_device - 'a'].major,
+            boot_devs[boot_device - 'a'].minor,
+            mem_size >> 20);
+#else
+    sprintf(p + 0x1000, "console=ttyS0,9600 console=tty0 root=%s mem=%dM",
+            boot_devs[boot_device - 'a'].name,
+            mem_size >> 20);
+#endif
+    env->gpr[6] = (uint32_t)p + 0x1000 - (uint32_t)phys_ram_base;
+    env->gpr[7] = env->gpr[6] + strlen(p + 0x1000);
+    if (loglevel > 0) {
+        fprintf(logfile, "cmdline: %p 0x%08x [%s]\n",
+                p + 0x1000, env->gpr[6], p + 0x1000);
+    } else {
+        printf("cmdline: %p 0x%08x [%s]\n",
+               p + 0x1000, env->gpr[6], p + 0x1000);
+    }
+    /* BI_FIRST */
+    p = set_bootinfo_tag(p, 0x1010, 0, 0);
+    /* BI_CMD_LINE */
+    p = set_bootinfo_tag(p, 0x1012, env->gpr[7] - env->gpr[6],
+                         (void *)(env->gpr[6] + (uint32_t)phys_ram_base));
+    /* BI_MEM_SIZE */
+    tmp = (void *)tmpi;
+    tmp[0] = (mem_size >> 24) & 0xFF;
+    tmp[1] = (mem_size >> 16) & 0xFF;
+    tmp[2] = (mem_size >> 8) & 0xFF;
+    tmp[3] = mem_size & 0xFF;
+    p = set_bootinfo_tag(p, 0x1017, 4, tmpi);
+    /* BI_INITRD */
+    tmp[0] = (env->gpr[4] >> 24) & 0xFF;
+    tmp[1] = (env->gpr[4] >> 16) & 0xFF;
+    tmp[2] = (env->gpr[4] >> 8) & 0xFF;
+    tmp[3] = env->gpr[4] & 0xFF;
+    tmp[4] = (env->gpr[5] >> 24) & 0xFF;
+    tmp[5] = (env->gpr[5] >> 16) & 0xFF;
+    tmp[6] = (env->gpr[5] >> 8) & 0xFF;
+    tmp[7] = env->gpr[5] & 0xFF;
+    p = set_bootinfo_tag(p, 0x1014, 8, tmpi);
+    env->gpr[4] = env->gpr[5] = 0;
+    /* BI_LAST */
+    p = set_bootinfo_tag(p, 0x1011, 0, 0);
+#else
+    /* Set up MMU:
+     * kernel is loaded at kernel_addr and wants to be seen at 0x01000000
+     */
+    setup_BAT(env, 0, 0x01000000, kernel_addr, 0x00400000, 1, 0, 2);
+    {
+#if 0
+        uint32_t offset = 
+            *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
+#else
+        uint32_t offset = 12;
+#endif
+        env->nip = 0x01000000 | (kernel_addr + offset);
+        printf("Start address: 0x%08x\n", env->nip);
+    }
+    env->gpr[1] = env->nip + (1 << 22);
+    p = (void *)(phys_ram_base + stack_addr);
+    put_long(p - 32, stack_addr);
+    env->gpr[1] -= 32;
+    printf("Kernel starts at 0x%08x stack 0x%08x\n", env->nip, env->gpr[1]);
+    /* We want all lower address not to be translated */
+    setup_BAT(env, 1, 0x00000000, 0x00000000, 0x010000000, 1, 1, 2);
+    /* We also need a BAT to access OF */
+    setup_BAT(env, 2, 0xFFFE0000, mem_size - 131072, 131072, 1, 0, 1);
+    /* Setup OF entry point */
+    {
+        char *p;
+        p = (char *)phys_ram_base + mem_size - 131072;
+        /* Special opcode to call OF */
+        *p++ = 0x18; *p++ = 0x00; *p++ = 0x00; *p++ = 0x02;
+        /* blr */
+        *p++ = 0x4E; *p++ = 0x80; *p++ = 0x00; *p++ = 0x20;
+    }
+    env->gpr[5] = 0xFFFE0000;
+    /* Register translations */
+    {
+        OF_transl_t translations[3] = {
+            { 0x01000000, 0x00400000, kernel_addr, 0x00000002, },
+            { 0x00000000, 0x01000000, 0x00000000, 0x00000002, },
+            { 0xFFFE0000, 0x00020000, mem_size - (128 * 1024),
+              0x00000001, },
+        };
+        OF_register_translations(3, translations);
+    }
+    /* Quite artificial, for now */
+    OF_register_bus("isa", "isa");
+    OF_register_serial("isa", "serial", 4, 0x3f8);
+    OF_register_stdio("serial", "serial");
+    /* Set up RTAS service */
+    RTAS_init();
+    /* Command line: let's put it just over the stack */
+#if 0
+#if 0
+    p = (void *)(((uint32_t)phys_ram_base + kernel_addr +
+                  kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1));
+#else
+    p = (void *)((uint32_t)phys_ram_base + kernel_addr + 0x400000);
+#endif
+#if 1
+    sprintf(p, "console=ttyS0,9600 root=%02x%02x mem=%dM",
+            boot_devs[boot_device - 'a'].major,
+            boot_devs[boot_device - 'a'].minor,
+            mem_size >> 20);
+#else
+    sprintf(p, "console=ttyS0,9600 root=%s mem=%dM ne2000=0x300,9",
+            boot_devs[boot_device - 'a'].name,
+            mem_size >> 20);
+#endif
+    OF_register_bootargs(p);
+#endif
+#endif
+}
+
+void PPC_end_init (void)
+{
+    VGA_init();
+}
+
+/* PC hardware initialisation */
+void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
+		   DisplayState *ds, const char **fd_filename, int snapshot,
+		   const char *kernel_filename, const char *kernel_cmdline,
+		   const char *initrd_filename)
+{
+    char buf[1024];
+    int PPC_io_memory;
+    int ret, linux_boot, initrd_size, i, nb_nics1, fd;
+
+    linux_boot = (kernel_filename != NULL);
+
+    /* allocate RAM */
+    cpu_register_physical_memory(0, ram_size, 0);
+
+    if (linux_boot) {
+        /* now we can load the kernel */
+        ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
+        if (ret < 0) {
+            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
+                    kernel_filename);
+            exit(1);
+        }
+        /* load initrd */
+        initrd_size = 0;
+#if 0
+        if (initrd_filename) {
+            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
+            if (initrd_size < 0) {
+                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
+                        initrd_filename);
+                exit(1);
+            }
+        }
+#endif
+        PPC_init_hw(/*env,*/ ram_size, KERNEL_LOAD_ADDR, ret,
+                    KERNEL_STACK_ADDR, boot_device, initrd_filename);
+    } else {
+	/* allocate ROM */
+	//        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+	snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME);
+	printf("load BIOS at %p\n", phys_ram_base + 0x000f0000);
+	ret = load_image(buf, phys_ram_base + 0x000f0000);
+	if (ret != 0x10000) {
+	    fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
+		    buf, ret);
+	    exit(1);
+	}
+    }
+
+    /* init basic PC hardware */
+    vga_initialize(ds, phys_ram_base + ram_size, ram_size, 
+                   vga_ram_size);
+    rtc_init(0x70, 8);
+    pic_init();
+    //    pit_init(0x40, 0);
+
+    fd = serial_open_device();
+    serial_init(0x3f8, 4, fd);
+#if 1
+    nb_nics1 = nb_nics;
+    if (nb_nics1 > NE2000_NB_MAX)
+        nb_nics1 = NE2000_NB_MAX;
+    for(i = 0; i < nb_nics1; i++) {
+        ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
+    }
+#endif
+
+    for(i = 0; i < 2; i++) {
+        ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
+                 bs_table[2 * i], bs_table[2 * i + 1]);
+    }
+    kbd_init();
+    AUD_init();
+    DMA_init();
+    //    SB16_init();
+
+    fdctrl_init(6, 2, 0, 0x3f0, fd_table);
+
+    /* Register 64 kB of IO space */
+    PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
+    cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
+    /* Register fake IO ports for PREP */
+    register_ioport_read(0x398, 2, 1, &PREP_io_read, NULL);
+    register_ioport_write(0x398, 2, 1, &PREP_io_write, NULL);
+    /* System control ports */
+    register_ioport_write(0x0092, 0x1, 1, &PREP_io_800_writeb, NULL);
+    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, NULL);
+    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, NULL);
+    /* PCI intack location (0xfef00000 / 0xbffffff0) */
+    PPC_io_memory = cpu_register_io_memory(0, PPC_ioB_read, PPC_ioB_write);
+    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
+    //    cpu_register_physical_memory(0xFEF00000, 0x4, PPC_io_memory);
+    prep_NVRAM_init();
+
+    PPC_end_init();
+}