find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162

51 files changed, 246 insertions, 246 deletions

diff --git a/hw/acpi.c b/hw/acpi.c
index add8cc8..37fadaa 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -87,7 +87,7 @@ static void pm_update_sci(PIIX4PMState *s)
 {
     int sci_level, pmsts;
     int64_t expire_time;
-   
+
     pmsts = get_pmsts(s);
     sci_level = (((pmsts & s->pmen) &
                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
@@ -239,7 +239,7 @@ static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 {
     PIIX4PMState *s = opaque;
     uint32_t val;
-   
+
     addr &= 1;
     if (addr == 0) {
         val = s->apmc;
@@ -480,9 +480,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
     pci_conf[0x0b] = 0x06; // bridge device
     pci_conf[0x0e] = 0x00; // header_type
     pci_conf[0x3d] = 0x01; // interrupt pin 1
-   
+
     pci_conf[0x40] = 0x01; /* PM io base read only bit */
-   
+
     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 
diff --git a/hw/adb.c b/hw/adb.c
index 756c079..1e43792 100644
--- a/hw/adb.c
+++ b/hw/adb.c
@@ -299,31 +299,31 @@ static int adb_mouse_poll(ADBDevice *d, uint8_t *obuf)
     if (s->last_buttons_state == s->buttons_state &&
         s->dx == 0 && s->dy == 0)
         return 0;
-       
+
     dx = s->dx;
     if (dx < -63)
         dx = -63;
     else if (dx > 63)
         dx = 63;
-   
+
     dy = s->dy;
     if (dy < -63)
         dy = -63;
     else if (dy > 63)
         dy = 63;
-   
+
     s->dx -= dx;
     s->dy -= dy;
     s->last_buttons_state = s->buttons_state;
-   
+
     dx &= 0x7f;
     dy &= 0x7f;
-   
+
     if (!(s->buttons_state & MOUSE_EVENT_LBUTTON))
         dy |= 0x80;
     if (!(s->buttons_state & MOUSE_EVENT_RBUTTON))
         dx |= 0x80;
-   
+
     obuf[0] = dy;
     obuf[1] = dx;
     return 2;
@@ -334,7 +334,7 @@ static int adb_mouse_request(ADBDevice *d, uint8_t *obuf,
 {
     MouseState *s = d->opaque;
     int cmd, reg, olen;
-   
+
     if ((buf[0] & 0x0f) == ADB_FLUSH) {
         /* flush mouse fifo */
         s->buttons_state = s->last_buttons_state;
diff --git a/hw/alpha_palcode.c b/hw/alpha_palcode.c
index 8df7d89..da2d9ad 100644
--- a/hw/alpha_palcode.c
+++ b/hw/alpha_palcode.c
@@ -937,7 +937,7 @@ static int paddr_from_pte (uint64_t *paddr, int *zbitsp, int *prot,
         }
     }
     *paddr = (pfn << page_bits) | (vaddr & page_mask);
-   
+
     return 0;
 }
 
diff --git a/hw/apic.c b/hw/apic.c
index bbe44fa..9e0f476 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -222,7 +222,7 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
             foreach_apic(apic_iter, deliver_bitmask,
                          apic_init_ipi(apic_iter) );
             return;
-   
+
         case APIC_DM_EXTINT:
             /* handled in I/O APIC code */
             break;
@@ -471,7 +471,7 @@ int apic_get_interrupt(CPUState *env)
         return -1;
     if (!(s->spurious_vec & APIC_SV_ENABLE))
         return -1;
-   
+
     /* XXX: spurious IRQ handling */
     intno = get_highest_priority_int(s->irr);
     if (intno < 0)
@@ -505,7 +505,7 @@ static uint32_t apic_get_current_count(APICState *s)
 static void apic_timer_update(APICState *s, int64_t current_time)
 {
     int64_t next_time, d;
-   
+
     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
         d = (current_time - s->initial_count_load_time) >>
             s->count_shift;
@@ -834,7 +834,7 @@ int apic_init(CPUState *env)
 
     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
     qemu_register_reset(apic_reset, s);
-   
+
     local_apics[s->id] = s;
     return 0;
 }
@@ -868,7 +868,7 @@ static void ioapic_service(IOAPICState *s)
                     vector = pic_read_irq(isa_pic);
                 else
                     vector = entry & 0xff;
-               
+
                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
                 apic_bus_deliver(deliver_bitmask, delivery_mode,
                                  vector, polarity, trig_mode);
@@ -1042,6 +1042,6 @@ IOAPICState *ioapic_init(void)
 
     register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
     qemu_register_reset(ioapic_reset, s);
-   
+
     return s;
 }
diff --git a/hw/cdrom.c b/hw/cdrom.c
index 18c7e31..4f1fce1 100644
--- a/hw/cdrom.c
+++ b/hw/cdrom.c
@@ -41,7 +41,7 @@ int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track)
 {
     uint8_t *q;
     int len;
-   
+
     if (start_track > 1 && start_track != 0xaa)
         return -1;
     q = buf + 2;
@@ -85,7 +85,7 @@ int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num)
 {
     uint8_t *q;
     int len;
-   
+
     q = buf + 2;
     *q++ = 1; /* first session */
     *q++ = 1; /* last session */
@@ -101,7 +101,7 @@ int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num)
     *q++ = 1; /* first track */
     *q++ = 0x00; /* disk type */
     *q++ = 0x00;
-   
+
     *q++ = 1; /* session number */
     *q++ = 0x14; /* data track */
     *q++ = 0; /* track number */
@@ -113,7 +113,7 @@ int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num)
     *q++ = 1; /* last track */
     *q++ = 0x00;
     *q++ = 0x00;
-   
+
     *q++ = 1; /* session number */
     *q++ = 0x14; /* data track */
     *q++ = 0; /* track number */
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index febac44..85bf4a2 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -275,7 +275,7 @@ typedef struct PCICirrusVGAState {
 } PCICirrusVGAState;
 
 static uint8_t rop_to_index[256];
-   
+
 /***************************************
  *
  *  prototypes.
@@ -788,7 +788,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
 {
     int copy_count;
     uint8_t *end_ptr;
-   
+
     if (s->cirrus_srccounter > 0) {
         if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
             cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
@@ -1148,7 +1148,7 @@ static int cirrus_get_bpp(VGAState *s1)
 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
 {
     int width, height;
-   
+
     width = (s->cr[0x01] + 1) * 8;
     height = s->cr[0x12] |
         ((s->cr[0x07] & 0x02) << 7) |
@@ -2223,7 +2223,7 @@ static void cirrus_cursor_invalidate(VGAState *s1)
         s->last_hw_cursor_y != s->hw_cursor_y) {
 
         invalidate_cursor1(s);
-       
+
         s->last_hw_cursor_size = size;
         s->last_hw_cursor_x = s->hw_cursor_x;
         s->last_hw_cursor_y = s->hw_cursor_y;
@@ -2240,7 +2240,7 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
     unsigned int color0, color1;
     const uint8_t *palette, *src;
     uint32_t content;
-   
+
     if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
         return;
     /* fast test to see if the cursor intersects with the scan line */
@@ -2252,7 +2252,7 @@ static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
     if (scr_y < s->hw_cursor_y ||
         scr_y >= (s->hw_cursor_y + h))
         return;
-   
+
     src = s->vram_ptr + s->real_vram_size - 16 * 1024;
     if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
         src += (s->sr[0x13] & 0x3c) * 256;
@@ -2379,7 +2379,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
     unsigned mode;
 
     addr &= s->cirrus_addr_mask;
-       
+
     if (((s->sr[0x17] & 0x44) == 0x44) &&
         ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
 	/* memory-mapped I/O */
@@ -2600,7 +2600,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
 	} else if (s->gr[0x0B] & 0x02) {
             goto generic_io;
         }
-       
+
 	mode = s->gr[0x05] & 0x7;
 	if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
             s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
@@ -3190,7 +3190,7 @@ void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
     CirrusVGAState *s;
 
     s = qemu_mallocz(sizeof(CirrusVGAState));
-   
+
     vga_common_init((VGAState *)s,
                     ds, vga_ram_base, vga_ram_offset, vga_ram_size);
     cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
@@ -3231,7 +3231,7 @@ void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
     uint8_t *pci_conf;
     CirrusVGAState *s;
     int device_id;
-   
+
     device_id = CIRRUS_ID_CLGD5446;
 
     /* setup PCI configuration registers */
diff --git a/hw/cirrus_vga_rop2.h b/hw/cirrus_vga_rop2.h
index 91f0db8..137681e 100644
--- a/hw/cirrus_vga_rop2.h
+++ b/hw/cirrus_vga_rop2.h
@@ -34,7 +34,7 @@
 #define PUTPIXEL()    ROP_OP(((uint32_t *)d)[0], col)
 #else
 #error unsupported DEPTH
-#endif               
+#endif
 
 static void
 glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH)
diff --git a/hw/cuda.c b/hw/cuda.c
index 75ceea1..7312bbd 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -116,10 +116,10 @@ typedef struct CUDAState {
     uint8_t anh;    /* A-side data, no handshake */
 
     CUDATimer timers[2];
-   
+
     uint8_t last_b; /* last value of B register */
     uint8_t last_acr; /* last value of B register */
-   
+
     int data_in_size;
     int data_in_index;
     int data_out_index;
@@ -196,7 +196,7 @@ static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
         counter = (d - (s->counter_value + 1)) % (s->latch + 2);
         counter = (s->latch - counter) & 0xffff;
     }
-   
+
     /* Note: we consider the irq is raised on 0 */
     if (counter == 0xffff) {
         next_time = d + s->latch + 1;
@@ -317,7 +317,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     CUDAState *s = opaque;
-   
+
     addr = (addr >> 9) & 0xf;
 #ifdef DEBUG_CUDA
     printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
diff --git a/hw/esp.c b/hw/esp.c
index 0d22ce3..943a159 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -531,7 +531,7 @@ static void esp_save(QEMUFile *f, void *opaque)
 static int esp_load(QEMUFile *f, void *opaque, int version_id)
 {
     ESPState *s = opaque;
-   
+
     if (version_id != 3)
         return -EINVAL; // Cannot emulate 2
 
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index a2f938c..fb46051 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -118,12 +118,12 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
     d->config[0x1a] = 0x00;  // subordinate_bus
     d->config[0x1c] = 0x00;
     d->config[0x1d] = 0x00;
-   
+
     d->config[0x20] = 0x00; // memory_base
     d->config[0x21] = 0x00;
     d->config[0x22] = 0x01; // memory_limit
     d->config[0x23] = 0x00;
-   
+
     d->config[0x24] = 0x00; // prefetchable_memory_base
     d->config[0x25] = 0x00;
     d->config[0x26] = 0x00; // prefetchable_memory_limit
@@ -145,12 +145,12 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
     d->config[0x1a] = 0x1;  // subordinate_bus
     d->config[0x1c] = 0x10; // io_base
     d->config[0x1d] = 0x20; // io_limit
-   
+
     d->config[0x20] = 0x80; // memory_base
     d->config[0x21] = 0x80;
     d->config[0x22] = 0x90; // memory_limit
     d->config[0x23] = 0x80;
-   
+
     d->config[0x24] = 0x00; // prefetchable_memory_base
     d->config[0x25] = 0x84;
     d->config[0x26] = 0x00; // prefetchable_memory_limit
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 26821e8..fbebbbe 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -287,10 +287,10 @@ static void gt64120_pci_mapping(GT64120State *s)
     /* Update IO mapping */
     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
     {
-      /* Unmap old IO address */	   
+      /* Unmap old IO address */
       if (s->PCI0IO_length)
       {
-        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);	    
+        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
       }
       /* Map new IO address */
       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index a31d24b..96eb656 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
     HeathrowPIC *pic;
     unsigned int n;
     uint32_t value;
-   
+
     n = ((addr & 0xfff) - 0x10) >> 4;
     if (n >= 2) {
         value = 0;
@@ -159,7 +159,7 @@ static void heathrow_pic_set_irq(void *opaque, int num, int level)
 qemu_irq *heathrow_pic_init(int *pmem_index)
 {
     HeathrowPICS *s;
-   
+
     s = qemu_mallocz(sizeof(HeathrowPICS));
     s->pics[0].level_triggered = 0;
     s->pics[1].level_triggered = 0x1ff00000;
diff --git a/hw/i8254.c b/hw/i8254.c
index db8a1b9..54407de 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -309,7 +309,7 @@ static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
     PITState *pit = opaque;
     int ret, count;
     PITChannelState *s;
-   
+
     addr &= 3;
     s = &pit->channels[addr];
     if (s->status_latched) {
@@ -391,7 +391,7 @@ static void pit_save(QEMUFile *f, void *opaque)
     PITState *pit = opaque;
     PITChannelState *s;
     int i;
-   
+
     for(i = 0; i < 3; i++) {
         s = &pit->channels[i];
         qemu_put_be32s(f, &s->count);
@@ -419,7 +419,7 @@ static int pit_load(QEMUFile *f, void *opaque, int version_id)
     PITState *pit = opaque;
     PITChannelState *s;
     int i;
-   
+
     if (version_id != 1)
         return -EINVAL;
 
diff --git a/hw/i8259.c b/hw/i8259.c
index 09aabe2..7c94d8d 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -155,7 +155,7 @@ void pic_update_irq(PicState2 *s)
                 printf("pic%d: imr=%x irr=%x padd=%d\n",
                        i, s->pics[i].imr, s->pics[i].irr,
                        s->pics[i].priority_add);
-               
+
             }
         }
         printf("pic: cpu_interrupt\n");
@@ -243,7 +243,7 @@ int pic_read_irq(PicState2 *s)
         intno = s->pics[0].irq_base + irq;
     }
     pic_update_irq(s);
-       
+
 #ifdef DEBUG_IRQ_LATENCY
     printf("IRQ%d latency=%0.3fus\n",
            irq,
@@ -429,7 +429,7 @@ uint32_t pic_intack_read(PicState2 *s)
         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
     /* Prepare for ISR read */
     s->pics[0].read_reg_select = 1;
-   
+
     return ret;
 }
 
@@ -448,7 +448,7 @@ static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 static void pic_save(QEMUFile *f, void *opaque)
 {
     PicState *s = opaque;
-   
+
     qemu_put_8s(f, &s->last_irr);
     qemu_put_8s(f, &s->irr);
     qemu_put_8s(f, &s->imr);
@@ -470,7 +470,7 @@ static void pic_save(QEMUFile *f, void *opaque)
 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 {
     PicState *s = opaque;
-   
+
     if (version_id != 1)
         return -EINVAL;
 
@@ -510,7 +510,7 @@ void pic_info(void)
 {
     int i;
     PicState *s;
-   
+
     if (!isa_pic)
         return;
 
diff --git a/hw/ide.c b/hw/ide.c
index c3b0e11..329d053 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -392,7 +392,7 @@ typedef struct BMDMAState {
     uint8_t cmd;
     uint8_t status;
     uint32_t addr;
-   
+
     struct PCIIDEState *pci_dev;
     /* current transfer state */
     uint32_t cur_addr;
@@ -469,7 +469,7 @@ static void ide_identify(IDEState *s)
     put_le16(p + 22, 4); /* ecc bytes */
     padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
     padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
-#if MAX_MULT_SECTORS > 1   
+#if MAX_MULT_SECTORS > 1
     put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
 #endif
     put_le16(p + 48, 1); /* dword I/O */
@@ -923,7 +923,7 @@ static void ide_sector_write(IDEState *s)
         ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
     }
     ide_set_sector(s, sector_num + n);
-   
+
     bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
 			       ide_sector_write_aio_cb, bm);
 }
@@ -1246,7 +1246,7 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
         bm->aiocb = NULL;
         return;
     }
-   
+
     s->io_buffer_index = 0;
     if (s->cd_sector_size == 2352) {
         n = 1;
@@ -1375,7 +1375,7 @@ static void ide_atapi_cmd(IDEState *s)
                     buf[9] = 0x12;
                     buf[10] = 0x08;
                     buf[11] = 0x00;
-                   
+
                     buf[12] = 0x70;
                     buf[13] = 3 << 5;
                     buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
@@ -1501,7 +1501,7 @@ static void ide_atapi_cmd(IDEState *s)
             int start, eject;
             start = packet[4] & 1;
             eject = (packet[4] >> 1) & 1;
-           
+
             if (eject && !start) {
                 /* eject the disk */
                 bdrv_eject(s->bs, 1);
@@ -2330,7 +2330,7 @@ static uint32_t ide_data_readl(void *opaque, uint32_t addr)
     IDEState *s = ((IDEState *)opaque)->cur_drive;
     uint8_t *p;
     int ret;
-   
+
     p = s->data_ptr;
     ret = cpu_to_le32(*(uint32_t *)p);
     p += 4;
@@ -2509,7 +2509,7 @@ static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
         register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
         register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
     }
-   
+
     /* data ports */
     register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
     register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
@@ -2584,7 +2584,7 @@ void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
     ide_state = qemu_mallocz(sizeof(IDEState) * 2);
     if (!ide_state)
         return;
-   
+
     ide_init2(ide_state, hd0, hd1, irq);
     ide_init_ioport(ide_state, iobase, iobase2);
 }
@@ -2671,7 +2671,7 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
     BMDMAState *bm = opaque;
     PCIIDEState *pci_dev;
     uint32_t val;
-   
+
     switch(addr & 3) {
     case 0:
         val = bm->cmd;
@@ -2835,7 +2835,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
     pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
     pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
     pci_conf[0x0e] = 0x00; // header_type
-   
+
     if (secondary_ide_enabled) {
         /* XXX: if not enabled, really disable the seconday IDE controller */
         pci_conf[0x51] = 0x80; /* enable IDE1 */
@@ -2853,7 +2853,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
                            PCI_ADDRESS_SPACE_IO, bmdma_map);
 
     pci_conf[0x3d] = 0x01; // interrupt on pin 1
-   
+
     for(i = 0; i < 4; i++)
         d->ide_if[i].pci_dev = (PCIDevice *)d;
 
@@ -2945,7 +2945,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 {
     PCIIDEState *d;
     uint8_t *pci_conf;
-   
+
     /* register a function 1 of PIIX3 */
     d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
                                            sizeof(PCIIDEState),
@@ -3133,7 +3133,7 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
 
     ide_if = qemu_mallocz(sizeof(IDEState) * 2);
     ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
-   
+
     pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
                                              pmac_ide_write, &ide_if[0]);
     return pmac_ide_memory;
diff --git a/hw/iommu.c b/hw/iommu.c
index bd52454..c36178c 100644
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -279,7 +279,7 @@ static void iommu_save(QEMUFile *f, void *opaque)
 {
     IOMMUState *s = opaque;
     int i;
-   
+
     for (i = 0; i < IOMMU_NREGS; i++)
 	qemu_put_be32s(f, &s->regs[i]);
     qemu_put_be64s(f, &s->iostart);
@@ -289,7 +289,7 @@ static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 {
     IOMMUState *s = opaque;
     int i;
-   
+
     if (version_id != 2)
         return -EINVAL;
 
@@ -322,7 +322,7 @@ void *iommu_init(target_phys_addr_t addr)
 
     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
-   
+
     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
     qemu_register_reset(iommu_reset, s);
     return s;
diff --git a/hw/m48t59.c b/hw/m48t59.c
index e097a7c..c2c0dec 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -90,7 +90,7 @@ static void get_time (m48t59_t *NVRAM, struct tm *tm)
 static void set_time (m48t59_t *NVRAM, struct tm *tm)
 {
     time_t now, new_time;
-   
+
     new_time = mktime(tm);
     now = time(NULL);
     NVRAM->time_offset = new_time - now;
@@ -510,7 +510,7 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
-   
+
     addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, value & 0xff);
 }
@@ -518,7 +518,7 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
-   
+
     addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
     m48t59_write(NVRAM, addr + 1, value & 0xff);
@@ -527,7 +527,7 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 {
     m48t59_t *NVRAM = opaque;
-   
+
     addr -= NVRAM->mem_base;
     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@@ -539,7 +539,7 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
 {
     m48t59_t *NVRAM = opaque;
     uint32_t retval;
-   
+
     addr -= NVRAM->mem_base;
     retval = m48t59_read(NVRAM, addr);
     return retval;
@@ -549,7 +549,7 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
 {
     m48t59_t *NVRAM = opaque;
     uint32_t retval;
-   
+
     addr -= NVRAM->mem_base;
     retval = m48t59_read(NVRAM, addr) << 8;
     retval |= m48t59_read(NVRAM, addr + 1);
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index 8d0da95..789ebd3 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -110,7 +110,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 #ifdef DEBUG_CMOS
         printf("cmos: write index=0x%02x val=0x%02x\n",
                s->cmos_index, data);
-#endif       
+#endif
         switch(s->cmos_index) {
         case RTC_SECONDS_ALARM:
         case RTC_MINUTES_ALARM:
@@ -283,7 +283,7 @@ static void rtc_update_second(void *opaque)
         qemu_mod_timer(s->second_timer, s->next_second_time);
     } else {
         rtc_next_second(&s->current_tm);
-       
+
         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
             /* update in progress bit */
             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
@@ -411,7 +411,7 @@ static void rtc_save(QEMUFile *f, void *opaque)
 
     qemu_put_buffer(f, s->cmos_data, 128);
     qemu_put_8s(f, &s->cmos_index);
-   
+
     qemu_put_be32s(f, &s->current_tm.tm_sec);
     qemu_put_be32s(f, &s->current_tm.tm_min);
     qemu_put_be32s(f, &s->current_tm.tm_hour);
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index ab4d3fd..3b37596 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -510,9 +510,9 @@ static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t
     stl_raw(p++, 0x00000000);                                      /* nop */
 
     /* YAMON service vector */
-    stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580);      /* start: */				
+    stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580);      /* start: */
     stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c);      /* print_count: */
-    stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580);      /* start: */				
+    stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580);      /* start: */
     stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800);      /* flush_cache: */
     stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808);      /* print: */
     stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800);      /* reg_cpu_isr: */
diff --git a/hw/ne2000.c b/hw/ne2000.c
index a5e0331..689216c 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -212,7 +212,7 @@ static int ne2000_buffer_full(NE2000State *s)
 static int ne2000_can_receive(void *opaque)
 {
     NE2000State *s = opaque;
-   
+
     if (s->cmd & E8390_STOP)
         return 1;
     return !ne2000_buffer_full(s);
@@ -228,14 +228,14 @@ static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
     uint8_t buf1[60];
     static const uint8_t broadcast_macaddr[6] =
         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-   
+
 #if defined(DEBUG_NE2000)
     printf("NE2000: received len=%d\n", size);
 #endif
 
     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
         return;
-   
+
     /* XXX: check this */
     if (s->rxcr & 0x10) {
         /* promiscuous: receive all */
@@ -252,10 +252,10 @@ static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
                 return;
         } else if (s->mem[0] == buf[0] &&
-                   s->mem[2] == buf[1] &&                  
-                   s->mem[4] == buf[2] &&           
-                   s->mem[6] == buf[3] &&           
-                   s->mem[8] == buf[4] &&           
+                   s->mem[2] == buf[1] &&
+                   s->mem[4] == buf[2] &&
+                   s->mem[6] == buf[3] &&
+                   s->mem[8] == buf[4] &&
                    s->mem[10] == buf[5]) {
             /* match */
         } else {
@@ -718,11 +718,11 @@ static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
 {
     NE2000State *s;
-   
+
     s = qemu_mallocz(sizeof(NE2000State));
     if (!s)
         return;
-   
+
     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 
@@ -749,7 +749,7 @@ void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
              s->macaddr[3],
              s->macaddr[4],
              s->macaddr[5]);
-            
+
     register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
 }
 
@@ -786,7 +786,7 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
     PCINE2000State *d;
     NE2000State *s;
     uint8_t *pci_conf;
-   
+
     d = (PCINE2000State *)pci_register_device(bus,
                                               "NE2000", sizeof(PCINE2000State),
                                               devfn,
@@ -800,7 +800,7 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
     pci_conf[0x0b] = 0x02;
     pci_conf[0x0e] = 0x00; // header_type
     pci_conf[0x3d] = 1; // interrupt pin 0
-   
+
     pci_register_io_region(&d->dev, 0, 0x100,
                            PCI_ADDRESS_SPACE_IO, ne2000_map);
     s = &d->ne2000;
@@ -819,7 +819,7 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
              s->macaddr[3],
              s->macaddr[4],
              s->macaddr[5]);
-            
+
     /* XXX: instance number ? */
     register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s);
 }
diff --git a/hw/openpic.c b/hw/openpic.c
index bd52828..54830c3 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -475,7 +475,7 @@ static uint32_t read_doorbell_register (openpic_t *opp,
 
     return retval;
 }
-    
+
 static void write_doorbell_register (penpic_t *opp, int n_dbl,
 				     uint32_t offset, uint32_t value)
 {
@@ -831,7 +831,7 @@ static uint32_t openpic_cpu_read (void *opaque, uint32_t addr)
     IRQ_dst_t *dst;
     uint32_t retval;
     int idx, n_IRQ;
-   
+
     DPRINTF("%s: addr %08x\n", __func__, addr);
     retval = 0xFFFFFFFF;
     if (addr & 0xF)
@@ -1005,7 +1005,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
     openpic_t *opp;
     uint8_t *pci_conf;
     int i, m;
-   
+
     /* XXX: for now, only one CPU is supported */
     if (nb_cpus != 1)
         return NULL;
@@ -1023,7 +1023,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
         pci_conf[0x0b] = 0x08;
         pci_conf[0x0e] = 0x00; // header_type
         pci_conf[0x3d] = 0x00; // no interrupt pin
-       
+
         /* Register I/O spaces */
         pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
                                PCI_ADDRESS_SPACE_MEM, &openpic_map);
@@ -1032,7 +1032,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
     }
     opp->mem_index = cpu_register_io_memory(0, openpic_read,
                                             openpic_write, opp);
-   
+
     //    isu_base &= 0xFFFC0000;
     opp->nb_cpus = nb_cpus;
     /* Set IRQ types */
diff --git a/hw/parallel.c b/hw/parallel.c
index 9558c3f..bda3f3a 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -88,7 +88,7 @@ static void
 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
 {
     ParallelState *s = opaque;
-   
+
     pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
 
     addr &= 7;
diff --git a/hw/pc.c b/hw/pc.c
index a4ce37e..ace0cee 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -182,7 +182,7 @@ static void cmos_init(int ram_size, int boot_device, BlockDriverState **hd_table
         val = 65535;
     rtc_set_memory(s, 0x34, val);
     rtc_set_memory(s, 0x35, val >> 8);
-   
+
     switch(boot_device) {
     case 'a':
     case 'b':
@@ -209,7 +209,7 @@ static void cmos_init(int ram_size, int boot_device, BlockDriverState **hd_table
 
     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
     rtc_set_memory(s, 0x10, val);
-   
+
     val = 0;
     nb = 0;
     if (fd0 < 3)
@@ -294,7 +294,7 @@ void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 {
     static const char shutdown_str[8] = "Shutdown";
     static int shutdown_index = 0;
-   
+
     switch(addr) {
         /* Bochs BIOS messages */
     case 0x400:
@@ -783,7 +783,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
     /* map all the bios at the top of memory */
     cpu_register_physical_memory((uint32_t)(-bios_size),
                                  bios_size, bios_offset | IO_MEM_ROM);
-   
+
     bochs_bios_init();
 
     if (linux_boot)
@@ -914,7 +914,7 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
         }
     }
-   
+
     if (i440fx_state) {
         i440fx_init_memory_mappings(i440fx_state);
     }
diff --git a/hw/pci.c b/hw/pci.c
index 55cdaa4..7e8adc4 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -105,7 +105,7 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 
     if (pci_irq_index >= PCI_DEVICES_MAX)
         return NULL;
-   
+
     if (devfn < 0) {
         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
             if (!bus->devices[devfn])
@@ -166,7 +166,7 @@ static void pci_update_mappings(PCIDevice *d)
     PCIIORegion *r;
     int cmd, i;
     uint32_t last_addr, new_addr, config_ofs;
-   
+
     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
     for(i = 0; i < PCI_NUM_REGIONS; i++) {
         r = &d->io_regions[i];
@@ -367,7 +367,7 @@ void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
     PCIBus *s = opaque;
     PCIDevice *pci_dev;
     int config_addr, bus_num;
-   
+
 #if defined(DEBUG_PCI) && 0
     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
            addr, val, len);
@@ -440,7 +440,7 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
     PCIDevice *pci_dev = (PCIDevice *)opaque;
     PCIBus *bus;
     int change;
-   
+
     change = level - pci_dev->irq_state[irq_num];
     if (!change)
         return;
@@ -556,7 +556,7 @@ void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
     PCIBus *bus = first_bus;
     PCIDevice *d;
     int devfn;
-   
+
     while (bus && bus->bus_num != bus_num)
         bus = bus->next;
     if (bus) {
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 9b036a6..ff4916d 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -338,7 +338,7 @@ static void kbd_reset(void *opaque)
 static void kbd_save(QEMUFile* f, void* opaque)
 {
     KBDState *s = (KBDState*)opaque;
-   
+
     qemu_put_8s(f, &s->write_cmd);
     qemu_put_8s(f, &s->status);
     qemu_put_8s(f, &s->mode);
@@ -348,7 +348,7 @@ static void kbd_save(QEMUFile* f, void* opaque)
 static int kbd_load(QEMUFile* f, void* opaque, int version_id)
 {
     KBDState *s = (KBDState*)opaque;
-   
+
     if (version_id != 3)
         return -EINVAL;
     qemu_get_8s(f, &s->write_cmd);
diff --git a/hw/pcnet.c b/hw/pcnet.c
index 11e8fe9..71a05da 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -731,7 +731,7 @@ static void pcnet_s_reset(PCNetState *s)
     s->rdra = 0;
     s->tdra = 0;
     s->rap = 0;
-   
+
     s->bcr[BCR_BSBC] &= ~0x0080;
 
     s->csr[0]   = 0x0004;
@@ -770,7 +770,7 @@ static void pcnet_update_irq(PCNetState *s)
 {
     int isr = 0;
     s->csr[0] &= ~0x0080;
-   
+
 #if 1
     if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
         (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
@@ -790,11 +790,11 @@ static void pcnet_update_irq(PCNetState *s)
         (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
 #endif
     {
-      
+
         isr = CSR_INEA(s);
         s->csr[0] |= 0x0080;
     }
-   
+
     if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
         s->csr[4] &= ~0x0080;
         s->csr[4] |= 0x0040;
@@ -834,7 +834,7 @@ static void pcnet_init(PCNetState *s)
 #ifdef PCNET_DEBUG
     printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
 #endif
-   
+
     if (BCR_SSIZE32(s)) {
         struct pcnet_initblk32 initblk;
         s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
@@ -898,7 +898,7 @@ static void pcnet_init(PCNetState *s)
         s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
 #endif
 
-    s->csr[0] |= 0x0101;   
+    s->csr[0] |= 0x0101;
     s->csr[0] &= ~0x0004;       /* clear STOP bit */
 }
 
@@ -910,7 +910,7 @@ static void pcnet_start(PCNetState *s)
 
     if (!CSR_DTX(s))
         s->csr[0] |= 0x0010;    /* set TXON */
-       
+
     if (!CSR_DRX(s))
         s->csr[0] |= 0x0020;    /* set RXON */
 
@@ -976,7 +976,7 @@ static void pcnet_rdte_poll(PCNetState *s)
 #endif
         }
     }
-   
+
     if (CSR_CRDA(s)) {
         struct pcnet_RMD rmd;
         RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
@@ -991,7 +991,7 @@ static void pcnet_rdte_poll(PCNetState *s)
     } else {
         CSR_CRBC(s) = CSR_CRST(s) = 0;
     }
-   
+
     if (CSR_NRDA(s)) {
         struct pcnet_RMD rmd;
         RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
@@ -1030,14 +1030,14 @@ static int pcnet_tdte_poll(PCNetState *s)
     if (CSR_CXDA(s)) {
         struct pcnet_TMD tmd;
 
-        TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));               
+        TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
 
         CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
         CSR_CXST(s) = tmd.status;
     } else {
         CSR_CXBC(s) = CSR_CXST(s) = 0;
     }
-   
+
     return !!(CSR_CXST(s) & 0x8000);
 }
 
@@ -1046,7 +1046,7 @@ static int pcnet_can_receive(void *opaque)
     PCNetState *s = opaque;
     if (CSR_STOP(s) || CSR_SPND(s))
         return 0;
-       
+
     if (s->recv_pos > 0)
         return 0;
 
@@ -1093,7 +1093,7 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
                 nrda = s->rdra +
                     (CSR_RCVRL(s) - rcvrc) *
                     (BCR_SWSTYLE(s) ? 16 : 8 );
-                RMDLOAD(&rmd, PHYSADDR(s,nrda));                 
+                RMDLOAD(&rmd, PHYSADDR(s,nrda));
                 if (GET_FIELD(rmd.status, RMDS, OWN)) {
 #ifdef PCNET_DEBUG_RMD
                     printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
@@ -1119,7 +1119,7 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
             int pktcount = 0;
 
             memcpy(src, buf, size);
-           
+
 #if 1
             /* no need to compute the CRC */
             src[size] = 0;
@@ -1136,7 +1136,7 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
                 while (size < 46) {
                     src[size++] = 0;
                 }
-               
+
                 while (p != &src[size]) {
                     CRC(fcs, *p++);
                 }
@@ -1178,7 +1178,7 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
                             PCNET_RECV_STORE();
                         }
                     }
-                }               
+                }
             }
 
 #undef PCNET_RECV_STORE
@@ -1203,22 +1203,22 @@ static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
 #endif
 #ifdef PCNET_DEBUG_RMD
             PRINT_RMD(&rmd);
-#endif       
+#endif
 
             while (pktcount--) {
                 if (CSR_RCVRC(s) <= 1)
                     CSR_RCVRC(s) = CSR_RCVRL(s);
                 else
-                    CSR_RCVRC(s)--;           
+                    CSR_RCVRC(s)--;
             }
-           
+
             pcnet_rdte_poll(s);
 
-        }       
+        }
     }
 
     pcnet_poll(s);
-    pcnet_update_irq(s);   
+    pcnet_update_irq(s);
 }
 
 static void pcnet_transmit(PCNetState *s)
@@ -1226,7 +1226,7 @@ static void pcnet_transmit(PCNetState *s)
     target_phys_addr_t xmit_cxda = 0;
     int count = CSR_XMTRL(s)-1;
     s->xmit_pos = -1;
-   
+
     if (!CSR_TXON(s)) {
         s->csr[0] &= ~0x0008;
         return;
@@ -1332,7 +1332,7 @@ static void pcnet_poll_timer(void *opaque)
         pcnet_transmit(s);
     }
 
-    pcnet_update_irq(s);   
+    pcnet_update_irq(s);
 
     if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
         uint64_t now = qemu_get_clock(vm_clock) * 33;
@@ -1592,11 +1592,11 @@ static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
     PCNetState *s = opaque;
 #ifdef PCNET_DEBUG
     printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
-#endif   
+#endif
     /* Check APROMWE bit to enable write access */
     if (pcnet_bcr_readw(s,2) & 0x80)
         s->prom[addr & 15] = val;
-}      
+}
 
 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
 {
@@ -1685,7 +1685,7 @@ static void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
         pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
 #ifdef PCNET_DEBUG_IO
         printf("device switched into dword i/o mode\n");
-#endif       
+#endif
     }
     pcnet_update_irq(s);
 }
@@ -1695,7 +1695,7 @@ static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
     PCNetState *s = opaque;
     uint32_t val = -1;
     pcnet_poll_timer(s);
-    if (BCR_DWIO(s)) { 
+    if (BCR_DWIO(s)) {
         switch (addr & 0x0f) {
         case 0x00: /* RDP */
             val = pcnet_csr_readw(s, s->rap);
@@ -1730,7 +1730,7 @@ static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
 
     register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
     register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
-   
+
     register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
     register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
     register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
@@ -1967,11 +1967,11 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
 
     d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
                                           devfn, NULL, NULL);
-                                         
+
     pci_conf = d->dev.config;
-   
+
     *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
-    *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);   
+    *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
     *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
     *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
     pci_conf[0x08] = 0x10;
@@ -1979,10 +1979,10 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
     pci_conf[0x0a] = 0x00; // ethernet network controller
     pci_conf[0x0b] = 0x02;
     pci_conf[0x0e] = 0x00; // header_type
-   
+
     *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
     *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
-   
+
     pci_conf[0x3d] = 1; // interrupt pin 0
     pci_conf[0x3e] = 0x06;
     pci_conf[0x3f] = 0xff;
@@ -1993,10 +1993,10 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
 
     pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
                            PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
-                          
+
     pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
                            PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
-                          
+
     d->irq = d->dev.irq[0];
     d->phys_mem_read = pci_physical_memory_read;
     d->phys_mem_write = pci_physical_memory_write;
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index 2545bcb..08f8890 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -222,7 +222,7 @@ static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
         offset -= (uint32_t)(long)pfl->storage;
     else
         offset -= pfl->base;
-       
+
     DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
             offset, value, width);
     /* Set the device in I/O access mode */
diff --git a/hw/pl011.c b/hw/pl011.c
index e66741b..94ed699 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -44,7 +44,7 @@ static const unsigned char pl011_id[] =
 static void pl011_update(pl011_state *s)
 {
     uint32_t flags;
-   
+
     flags = s->int_level & s->int_enabled;
     qemu_set_irq(s->irq, flags != 0);
 }
diff --git a/hw/pl110.c b/hw/pl110.c
index 3494264..061ec7a 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -117,7 +117,7 @@ static void pl110_update_display(void *opaque)
 
     if (!pl110_enabled(s))
         return;
-   
+
     switch (s->ds->depth) {
     case 0:
         return;
@@ -151,7 +151,7 @@ static void pl110_update_display(void *opaque)
       fn = fntable[s->bpp + 12];
     else
       fn = fntable[s->bpp];
-   
+
     src_width = s->cols;
     switch (s->bpp) {
     case BPP_1:
diff --git a/hw/pl181.c b/hw/pl181.c
index b450e58..a905cbb 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -177,7 +177,7 @@ error:
 /* Transfer data between the card and the FIFO.  This is complicated by
    the FIFO holding 32-bit words and the card taking data in single byte
    chunks.  FIFO bytes are transferred in little-endian order.  */
-  
+
 static void pl181_fifo_run(pl181_state *s)
 {
     uint32_t bits;
diff --git a/hw/ppc.c b/hw/ppc.c
index a901243..d0eb7a4 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -623,7 +623,7 @@ struct ppcemb_timer_t {
     uint64_t wdt_next;    /* Tick for next WDT interrupt  */
     struct QEMUTimer *wdt_timer;
 };
-  
+
 /* Fixed interval timer */
 static void cpu_4xx_fit_cb (void *opaque)
 {
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index cfb592e..69655d8 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -511,7 +511,7 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size, int boot_device,
     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
     int linux_boot;
     int fl_idx, fl_sectors;
-   
+
     /* RAM is soldered to the board so the size cannot be changed */
     ram_bases[0] = 0x00000000;
     ram_sizes[0] = 0x04000000;
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 1a6a666..dd13508 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -2212,7 +2212,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
         }
         mask = mask >> 1;
     }
-       
+
 }
 
 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
@@ -2228,7 +2228,7 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
             qemu_irq_lower(gpt->irqs[i]);
         mask = mask >> 1;
     }
-       
+
 }
 
 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c
index e5a6313..a5e67e0 100644
--- a/hw/ppc_chrp.c
+++ b/hw/ppc_chrp.c
@@ -173,7 +173,7 @@ static void macio_init(PCIBus *bus, int device_id)
     d->config[0x0e] = 0x00; // header_type
 
     d->config[0x3d] = 0x01; // interrupt on pin 1
-   
+
     dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
 
     pci_register_io_region(d, 0, 0x80000,
@@ -208,7 +208,7 @@ static int vga_osi_call(CPUState *env)
 {
     static int vga_vbl_enabled;
     int linesize;
-   
+
     //    printf("osi_call R5=%d\n", env->gpr[5]);
 
     /* same handler as PearPC, coming from the original MOL video
@@ -280,14 +280,14 @@ static uint8_t nvram_chksum(const uint8_t *buf, int n)
 void pmac_format_nvram_partition(uint8_t *buf, int len)
 {
     char partition_name[12] = "wwwwwwwwwwww";
-   
+
     buf[0] = 0x7f; /* free partition magic */
     buf[1] = 0; /* checksum */
     buf[2] = len >> 8;
     buf[3] = len;
     memcpy(buf + 4, partition_name, 12);
     buf[1] = nvram_chksum(buf, 16);
-}   
+}
 
 /* PowerPC CHRP hardware initialisation */
 static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
@@ -355,7 +355,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
     bios_size = (bios_size + 0xfff) & ~0xfff;
     cpu_register_physical_memory((uint32_t)(-bios_size),
                                  bios_size, bios_offset | IO_MEM_ROM);
-   
+
     /* allocate and load VGA BIOS */
     vga_bios_offset = bios_offset + bios_size;
     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
@@ -376,7 +376,7 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
         vga_bios_size += 8;
     }
     vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
-   
+
     if (linux_boot) {
         kernel_base = KERNEL_LOAD_ADDR;
         /* now we can load the kernel */
@@ -427,24 +427,24 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
 
         /* XXX: suppress that */
         dummy_irq = i8259_init(NULL);
-       
+
         /* XXX: use Mac Serial port */
         serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
-       
+
         for(i = 0; i < nb_nics; i++) {
             if (!nd_table[i].model)
                 nd_table[i].model = "ne2k_pci";
             pci_nic_init(pci_bus, &nd_table[i], -1);
         }
-       
+
         pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
 
         /* cuda also initialize ADB */
         cuda_mem_index = cuda_init(pic[0x12]);
-       
+
         adb_kbd_init(&adb_bus);
         adb_mouse_init(&adb_bus);
-       
+
         {
             MacIONVRAMState *nvr;
             nvr = macio_nvram_init();
@@ -534,14 +534,14 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
 #endif
         /* cuda also initialize ADB */
         cuda_mem_index = cuda_init(pic[0x19]);
-       
+
         adb_kbd_init(&adb_bus);
         adb_mouse_init(&adb_bus);
-       
+
         macio_init(pci_bus, 0x0022);
-       
+
         nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
-       
+
         arch_name = "MAC99";
     }
 
@@ -578,7 +578,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0);
 }
-   
+
 static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
                                DisplayState *ds, const char **fd_filename,
                                int snapshot,
diff --git a/hw/ps2.c b/hw/ps2.c
index 233ff54..5367df1 100644
--- a/hw/ps2.c
+++ b/hw/ps2.c
@@ -146,7 +146,7 @@ uint32_t ps2_read_data(void *opaque)
     PS2State *s = (PS2State *)opaque;
     PS2Queue *q;
     int val, index;
-   
+
     q = &s->queue;
     if (q->count == 0) {
         /* NOTE: if no data left, we return the last keyboard one
@@ -311,7 +311,7 @@ static void ps2_mouse_event(void *opaque,
         s->mouse_buttons == buttons_state)
 	return;
     s->mouse_buttons = buttons_state;
-   
+
     if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
         (s->common.queue.count < (PS2_QUEUE_SIZE - 16))) {
         for(;;) {
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 097ad47..a970eb3 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -890,10 +890,10 @@ static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int d
             ++s->tally_counters.RxOkMul;
 
         } else if (s->phys[0] == buf[0] &&
-                   s->phys[1] == buf[1] &&                  
-                   s->phys[2] == buf[2] &&           
-                   s->phys[3] == buf[3] &&           
-                   s->phys[4] == buf[4] &&           
+                   s->phys[1] == buf[1] &&
+                   s->phys[2] == buf[2] &&
+                   s->phys[3] == buf[3] &&
+                   s->phys[4] == buf[4] &&
                    s->phys[5] == buf[5]) {
             /* match */
             if (!(s->RxConfig & AcceptMyPhys))
@@ -2420,17 +2420,17 @@ static uint16_t rtl8139_TSAD_read(RTL8139State *s)
          |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
          |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
          |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
-        
+
          |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
          |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
          |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
          |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
-        
+
          |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
          |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
          |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
          |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
-      
+
 
     DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
 
@@ -3410,7 +3410,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
     PCIRTL8139State *d;
     RTL8139State *s;
     uint8_t *pci_conf;
-   
+
     d = (PCIRTL8139State *)pci_register_device(bus,
                                               "RTL8139", sizeof(PCIRTL8139State),
                                               devfn,
@@ -3458,7 +3458,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
     s->cplus_txbuffer = NULL;
     s->cplus_txbuffer_len = 0;
     s->cplus_txbuffer_offset = 0;
-            
+
     /* XXX: instance number ? */
     register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
 
diff --git a/hw/serial.c b/hw/serial.c
index ac3995b..36a7cc4 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -142,7 +142,7 @@ static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 {
     SerialState *s = opaque;
     unsigned char ch;
-   
+
     addr &= 7;
 #ifdef DEBUG_SERIAL
     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index 98cac6e..f604702 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -308,7 +308,7 @@ static void slavio_intctl_save(QEMUFile *f, void *opaque)
 {
     SLAVIO_INTCTLState *s = opaque;
     int i;
-   
+
     for (i = 0; i < MAX_CPUS; i++) {
 	qemu_put_be32s(f, &s->intreg_pending[i]);
     }
diff --git a/hw/slavio_serial.c b/hw/slavio_serial.c
index 990f5c7..71529b1 100644
--- a/hw/slavio_serial.c
+++ b/hw/slavio_serial.c
@@ -136,7 +136,7 @@ static uint32_t get_queue(void *opaque)
     ChannelState *s = opaque;
     SERIOQueue *q = &s->queue;
     int val;
-   
+
     if (q->count == 0) {
 	return 0;
     } else {
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index c9a3a56..d3c75bf 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -210,7 +210,7 @@ static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 {
     SLAVIO_TIMERState *s = opaque;
     uint32_t tmp;
-   
+
     if (version_id != 2)
         return -EINVAL;
 
diff --git a/hw/smbus_eeprom.c b/hw/smbus_eeprom.c
index 5b8637d..cf54c34 100644
--- a/hw/smbus_eeprom.c
+++ b/hw/smbus_eeprom.c
@@ -94,7 +94,7 @@ static uint8_t eeprom_read_data(SMBusDevice *dev, uint8_t cmd, int n)
 void smbus_eeprom_device_init(i2c_bus *bus, uint8_t addr, uint8_t *buf)
 {
     SMBusEEPROMDevice *eeprom;
-   
+
     eeprom = (SMBusEEPROMDevice *)smbus_device_init(bus, addr,
         sizeof(SMBusEEPROMDevice));
 
diff --git a/hw/smc91c111.c b/hw/smc91c111.c
index a6a11e0..b8d0cba 100644
--- a/hw/smc91c111.c
+++ b/hw/smc91c111.c
@@ -649,7 +649,7 @@ static void smc91c111_receive(void *opaque, const uint8_t *buf, int size)
     /* Pad short packets.  */
     if (size < 64) {
         int pad;
-       
+
         if (size & 1)
             *(p++) = buf[size - 1];
         pad = 64 - size;
diff --git a/hw/tcx.c b/hw/tcx.c
index 72c9bcd..9a72d6a 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -208,7 +208,7 @@ static void tcx_update_display(void *opaque)
     case 0:
 	return;
     }
-   
+
     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
 	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
 	    if (y_start < 0)
@@ -353,7 +353,7 @@ static void tcx24_invalidate_display(void *opaque)
 static void tcx_save(QEMUFile *f, void *opaque)
 {
     TCXState *s = opaque;
-   
+
     qemu_put_be16s(f, (uint16_t *)&s->height);
     qemu_put_be16s(f, (uint16_t *)&s->width);
     qemu_put_be16s(f, (uint16_t *)&s->depth);
diff --git a/hw/usb-hid.c b/hw/usb-hid.c
index e3b94d0..e0b2ba4 100644
--- a/hw/usb-hid.c
+++ b/hw/usb-hid.c
@@ -102,7 +102,7 @@ static const uint8_t qemu_mouse_config_descriptor[] = {
 				     5: Remote wakeup,
 				     4..0: resvd */
 	50,         /*  u8  MaxPower; */
-     
+
 	/* USB 1.1:
 	 * USB 2.0, single TT organization (mandatory):
 	 *	one interface, protocol 0
@@ -124,7 +124,7 @@ static const uint8_t qemu_mouse_config_descriptor[] = {
 	0x01,       /*  u8  if_bInterfaceSubClass; */
 	0x02,       /*  u8  if_bInterfaceProtocol; [usb1.1 or single tt] */
 	0x07,       /*  u8  if_iInterface; */
-    
+
         /* HID descriptor */
         0x09,        /*  u8  bLength; */
         0x21,        /*  u8 bDescriptorType; */
@@ -157,7 +157,7 @@ static const uint8_t qemu_tablet_config_descriptor[] = {
 				     5: Remote wakeup,
 				     4..0: resvd */
 	50,         /*  u8  MaxPower; */
-     
+
 	/* USB 1.1:
 	 * USB 2.0, single TT organization (mandatory):
 	 *	one interface, protocol 0
@@ -474,7 +474,7 @@ static int usb_mouse_poll(USBHIDState *hs, uint8_t *buf, int len)
                                                   0, "QEMU USB Mouse");
 	s->mouse_grabbed = 1;
     }
-   
+
     dx = int_clamp(s->dx, -128, 127);
     dy = int_clamp(s->dy, -128, 127);
     dz = int_clamp(s->dz, -128, 127);
@@ -482,7 +482,7 @@ static int usb_mouse_poll(USBHIDState *hs, uint8_t *buf, int len)
     s->dx -= dx;
     s->dy -= dy;
     s->dz -= dz;
-   
+
     b = 0;
     if (s->buttons_state & MOUSE_EVENT_LBUTTON)
         b |= 0x01;
@@ -490,7 +490,7 @@ static int usb_mouse_poll(USBHIDState *hs, uint8_t *buf, int len)
         b |= 0x02;
     if (s->buttons_state & MOUSE_EVENT_MBUTTON)
         b |= 0x04;
-   
+
     buf[0] = b;
     buf[1] = dx;
     buf[2] = dy;
@@ -512,7 +512,7 @@ static int usb_tablet_poll(USBHIDState *hs, uint8_t *buf, int len)
                                                   1, "QEMU USB Tablet");
 	s->mouse_grabbed = 1;
     }
-   
+
     dz = int_clamp(s->dz, -128, 127);
     s->dz -= dz;
 
diff --git a/hw/usb-hub.c b/hw/usb-hub.c
index bfdd5f9..1dcac3c 100644
--- a/hw/usb-hub.c
+++ b/hw/usb-hub.c
@@ -118,7 +118,7 @@ static const uint8_t qemu_hub_config_descriptor[] = {
 				     5: Remote wakeup,
 				     4..0: resvd */
 	0x00,       /*  u8  MaxPower; */
-     
+
 	/* USB 1.1:
 	 * USB 2.0, single TT organization (mandatory):
 	 *	one interface, protocol 0
@@ -140,7 +140,7 @@ static const uint8_t qemu_hub_config_descriptor[] = {
 	0x00,       /*  u8  if_bInterfaceSubClass; */
 	0x00,       /*  u8  if_bInterfaceProtocol; [usb1.1 or single tt] */
 	0x00,       /*  u8  if_iInterface; */
-    
+
 	/* one endpoint (status change endpoint) */
 	0x07,       /*  u8  ep_bLength; */
 	0x05,       /*  u8  ep_bDescriptorType; Endpoint */
@@ -167,11 +167,11 @@ static void usb_hub_attach(USBPort *port1, USBDevice *dev)
 {
     USBHubState *s = port1->opaque;
     USBHubPort *port = &s->ports[port1->index];
-   
+
     if (dev) {
         if (port->port.dev)
             usb_attach(port1, NULL);
-       
+
         port->wPortStatus |= PORT_STAT_CONNECTION;
         port->wPortChange |= PORT_STAT_C_CONNECTION;
         if (dev->speed == USB_SPEED_LOW)
diff --git a/hw/usb-msd.c b/hw/usb-msd.c
index f428916..b1ad9ec 100644
--- a/hw/usb-msd.c
+++ b/hw/usb-msd.c
@@ -99,7 +99,7 @@ static const uint8_t qemu_msd_config_descriptor[] = {
 				     5: Remote wakeup,
 				     4..0: resvd */
 	0x00,       /*  u8  MaxPower; */
-     
+
 	/* one interface */
 	0x09,       /*  u8  if_bLength; */
 	0x04,       /*  u8  if_bDescriptorType; Interface */
@@ -110,7 +110,7 @@ static const uint8_t qemu_msd_config_descriptor[] = {
 	0x06,       /*  u8  if_bInterfaceSubClass; SCSI */
 	0x50,       /*  u8  if_bInterfaceProtocol; Bulk Only */
 	0x00,       /*  u8  if_iInterface; */
-    
+
 	/* Bulk-In endpoint */
 	0x07,       /*  u8  ep_bLength; */
 	0x05,       /*  u8  ep_bDescriptorType; Endpoint */
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index cd04ad1..5867409 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -149,7 +149,7 @@ static void uhci_reset(UHCIState *s)
 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     UHCIState *s = opaque;
-   
+
     addr &= 0x1f;
     switch(addr) {
     case 0x0c:
@@ -178,7 +178,7 @@ static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 {
     UHCIState *s = opaque;
-   
+
     addr &= 0x1f;
 #ifdef DEBUG
     printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
@@ -458,7 +458,7 @@ static int uhci_handle_td(UHCIState *s, UHCI_TD *td, int *int_mask)
     if (td->ctrl & TD_CTRL_IOC) {
         *int_mask |= 0x01;
     }
-   
+
     if (!(td->ctrl & TD_CTRL_ACTIVE))
         return 1;
 
@@ -807,7 +807,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
     pci_conf[0x0e] = 0x00; // header_type
     pci_conf[0x3d] = 4; // interrupt pin 3
     pci_conf[0x60] = 0x10; // release number
-   
+
     for(i = 0; i < NB_PORTS; i++) {
         qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach);
     }
diff --git a/hw/usb.h b/hw/usb.h
index 17832cf..c5d24f1 100644
--- a/hw/usb.h
+++ b/hw/usb.h
@@ -119,7 +119,7 @@ struct USBDevice {
     void (*handle_destroy)(USBDevice *dev);
 
     int speed;
-   
+
     /* The following fields are used by the generic USB device
        layer. They are here just to avoid creating a new structure for
        them. */
@@ -129,7 +129,7 @@ struct USBDevice {
     int (*handle_data)(USBDevice *dev, USBPacket *p);
     uint8_t addr;
     char devname[32];
-   
+
     int state;
     uint8_t setup_buf[8];
     uint8_t data_buf[1024];
diff --git a/hw/vga.c b/hw/vga.c
index de74764..4c7d9ff 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -467,7 +467,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
                     s->vbe_regs[VBE_DISPI_INDEX_YRES];
                 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
                 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
-               
+
                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
                 else
@@ -480,7 +480,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
                     memset(s->vram_ptr, 0,
                            s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
                 }
-               
+
                 /* we initialize the VGA graphic mode (should be done
                    in BIOS) */
                 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
@@ -497,7 +497,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
                 s->cr[0x18] = 0xff;
                 s->cr[0x07] |= 0x10;
                 s->cr[0x09] |= 0x40;
-               
+
                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
                     shift_control = 0;
                     s->sr[0x01] &= ~8; /* no double line */
@@ -562,7 +562,7 @@ uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
     VGAState *s = opaque;
     int memory_map_mode, plane;
     uint32_t ret;
-   
+
     /* convert to VGA memory offset */
     memory_map_mode = (s->gr[6] >> 2) & 3;
     addr &= 0x1ffff;
@@ -586,7 +586,7 @@ uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
             return 0xff;
         break;
     }
-   
+
     if (s->sr[4] & 0x08) {
         /* chain 4 mode : simplest access */
         ret = s->vram_ptr[addr];
@@ -676,7 +676,7 @@ void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
             return;
         break;
     }
-   
+
     if (s->sr[4] & 0x08) {
         /* chain 4 mode : simplest access */
         plane = addr & 3;
@@ -961,7 +961,7 @@ static void vga_get_offsets(VGAState *s,
         line_compare = 65535;
     } else
 #endif
-    { 
+    {
         /* compute line_offset in bytes */
         line_offset = s->cr[0x13];
         line_offset <<= 3;
@@ -984,7 +984,7 @@ static int update_basic_params(VGAState *s)
 {
     int full_update;
     uint32_t start_addr, line_offset, line_compare;
-   
+
     full_update = 0;
 
     s->get_offsets(s, &line_offset, &start_addr, &line_compare);
@@ -1055,7 +1055,7 @@ static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
     vga_draw_glyph9_16,
     vga_draw_glyph9_16,
 };
-   
+
 static const uint8_t cursor_glyph[32 * 4] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -1073,7 +1073,7 @@ static const uint8_t cursor_glyph[32 * 4] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};   
+};
 
 /*
  * Text mode update
@@ -1098,7 +1098,7 @@ static void vga_draw_text(VGAState *s, int full_update)
 
     full_update |= update_palette16(s);
     palette = s->last_palette;
-   
+
     /* compute font data address (in plane 2) */
     v = s->sr[3];
     offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
@@ -1174,14 +1174,14 @@ static void vga_draw_text(VGAState *s, int full_update)
         s->cursor_end = s->cr[0xb];
     }
     cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
-   
+
     depth_index = get_depth_index(s->ds);
     if (cw == 16)
         vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
     else
         vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
     vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
-   
+
     dest = s->ds->data;
     linesize = s->ds->linesize;
     ch_attr_ptr = s->last_ch_attr;
@@ -1379,7 +1379,7 @@ static int vga_get_bpp(VGAState *s)
 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
 {
     int width, height;
-   
+
 #ifdef CONFIG_BOCHS_VBE
     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
         width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
@@ -1420,7 +1420,7 @@ static void vga_draw_graphic(VGAState *s, int full_update)
     uint8_t *d;
     uint32_t v, addr1, addr;
     vga_draw_line_func *vga_draw_line;
-   
+
     full_update |= update_basic_params(s);
 
     s->get_resolution(s, &width, &height);
@@ -1442,7 +1442,7 @@ static void vga_draw_graphic(VGAState *s, int full_update)
         s->shift_control = shift_control;
         s->double_scan = double_scan;
     }
-   
+
     if (shift_control == 0) {
         full_update |= update_palette16(s);
         if (s->sr[0x01] & 8) {
@@ -1497,7 +1497,7 @@ static void vga_draw_graphic(VGAState *s, int full_update)
     }
     if (s->cursor_invalidate)
         s->cursor_invalidate(s);
-   
+
     line_offset = s->line_offset;
 #if 0
     printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
@@ -1616,7 +1616,7 @@ static void vga_update_display(void *opaque)
     } else {
         s->rgb_to_pixel =
             rgb_to_pixel_dup_table[get_depth_index(s->ds)];
-       
+
         full_update = 0;
         if (!(s->ar_index & 0x20)) {
             graphic_mode = GMODE_BLANK;
@@ -1646,7 +1646,7 @@ static void vga_update_display(void *opaque)
 static void vga_invalidate_display(void *opaque)
 {
     VGAState *s = (VGAState *)opaque;
-   
+
     s->last_width = -1;
     s->last_height = -1;
 }
@@ -2009,21 +2009,21 @@ int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
     PCIVGAState *d;
     VGAState *s;
     uint8_t *pci_conf;
-   
+
     d = (PCIVGAState *)pci_register_device(bus, "VGA",
                                            sizeof(PCIVGAState),
                                            -1, NULL, NULL);
     if (!d)
         return -1;
     s = &d->vga_state;
-   
+
     vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
     vga_init(s);
 
     graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);
 
     s->pci_dev = &d->dev;
-   
+
     pci_conf = d->dev.config;
     pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
     pci_conf[0x01] = 0x12;
@@ -2032,7 +2032,7 @@ int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
     pci_conf[0x0a] = 0x00; // VGA controller
     pci_conf[0x0b] = 0x03;
     pci_conf[0x0e] = 0x00; // header_type
-   
+
     /* XXX: vga_ram_size must be a power of two */
     pci_register_io_region(&d->dev, 0, vga_ram_size,
                            PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
@@ -2107,7 +2107,7 @@ static void vga_screen_dump(void *opaque, const char *filename)
 {
     VGAState *s = (VGAState *)opaque;
     DisplayState *saved_ds, ds1, *ds = &ds1;
-   
+
     /* XXX: this is a little hackish */
     vga_invalidate_display(s);
     saved_ds = s->ds;
@@ -2121,7 +2121,7 @@ static void vga_screen_dump(void *opaque, const char *filename)
     s->ds = ds;
     s->graphic_mode = -1;
     vga_update_display(s);
-   
+
     if (ds->data) {
         ppm_save(filename, ds->data, vga_save_w, vga_save_h,
                  s->ds->linesize);
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 3eb4e29..a94162d 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -45,20 +45,20 @@
 #define VBE_DISPI_INDEX_X_OFFSET        0x8
 #define VBE_DISPI_INDEX_Y_OFFSET        0x9
 #define VBE_DISPI_INDEX_NB              0xa
-     
+
 #define VBE_DISPI_ID0                   0xB0C0
 #define VBE_DISPI_ID1                   0xB0C1
 #define VBE_DISPI_ID2                   0xB0C2
 #define VBE_DISPI_ID3                   0xB0C3
 #define VBE_DISPI_ID4                   0xB0C4
- 
+
 #define VBE_DISPI_DISABLED              0x00
 #define VBE_DISPI_ENABLED               0x01
 #define VBE_DISPI_GETCAPS               0x02
 #define VBE_DISPI_8BIT_DAC              0x20
 #define VBE_DISPI_LFB_ENABLED           0x40
 #define VBE_DISPI_NOCLEARMEM            0x80
- 
+
 #define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000
 
 #ifdef CONFIG_BOCHS_VBE
diff --git a/hw/vga_template.h b/hw/vga_template.h
index 41f6e25..0bc2e80 100644
--- a/hw/vga_template.h
+++ b/hw/vga_template.h
@@ -73,7 +73,7 @@ static void glue(vga_draw_glyph8_, DEPTH)(uint8_t *d, int linesize,
                                           uint32_t fgcol, uint32_t bgcol)
 {
     uint32_t font_data, xorcol;
-   
+
     xorcol = bgcol ^ fgcol;
     do {
         font_data = font_ptr[0];
@@ -88,7 +88,7 @@ static void glue(vga_draw_glyph16_, DEPTH)(uint8_t *d, int linesize,
                                           uint32_t fgcol, uint32_t bgcol)
 {
     uint32_t font_data, xorcol;
-   
+
     xorcol = bgcol ^ fgcol;
     do {
         font_data = font_ptr[0];
@@ -108,7 +108,7 @@ static void glue(vga_draw_glyph9_, DEPTH)(uint8_t *d, int linesize,
                                           uint32_t fgcol, uint32_t bgcol, int dup9)
 {
     uint32_t font_data, xorcol, v;
-   
+
     xorcol = bgcol ^ fgcol;
     do {
         font_data = font_ptr[0];
@@ -120,7 +120,7 @@ static void glue(vga_draw_glyph9_, DEPTH)(uint8_t *d, int linesize,
             ((uint8_t *)d)[8] = v >> (24 * (1 - BIG));
         else
             ((uint8_t *)d)[8] = bgcol;
-       
+
 #elif BPP == 2
         cpu_to_32wu(((uint32_t *)d)+0, (dmask4[(font_data >> 6)] & xorcol) ^ bgcol);
         cpu_to_32wu(((uint32_t *)d)+1, (dmask4[(font_data >> 4) & 3] & xorcol) ^ bgcol);
@@ -433,7 +433,7 @@ static void glue(vga_draw_line15_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
         s += 2;
         d += BPP;
     } while (--w != 0);
-#endif   
+#endif
 }
 
 /*
@@ -458,7 +458,7 @@ static void glue(vga_draw_line16_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
         s += 2;
         d += BPP;
     } while (--w != 0);
-#endif   
+#endif
 }
 
 /*