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| author | Bernhard Beschow <shentey@gmail.com> | 2023-10-28 14:24:12 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-11-02 13:36:45 +0000 |
| commit | bb2fc5b9958f183e63d839a6e6e10cdc4dad0981 (patch) | |
| tree | a2d3bf5345735f4491f12efc4964af70d41fe6e8 /hw | |
| parent | 88a9973e85f4a51a0270c760c03bf6707d8cb1fa (diff) | |
| download | qemu-bb2fc5b9958f183e63d839a6e6e10cdc4dad0981.zip qemu-bb2fc5b9958f183e63d839a6e6e10cdc4dad0981.tar.gz qemu-bb2fc5b9958f183e63d839a6e6e10cdc4dad0981.tar.bz2 | |
hw/misc/imx7_snvs: Trace MMIO access
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231028122415.14869-4-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/misc/imx7_snvs.c | 5 | ||||
| -rw-r--r-- | hw/misc/trace-events | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index ee7698b..a245f96 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -16,9 +16,12 @@ #include "hw/misc/imx7_snvs.h" #include "qemu/module.h" #include "sysemu/runstate.h" +#include "trace.h" static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) { + trace_imx7_snvs_read(offset, 0); + return 0; } @@ -28,6 +31,8 @@ static void imx7_snvs_write(void *opaque, hwaddr offset, const uint32_t value = v; const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + trace_imx7_snvs_write(offset, value); + if (offset == SNVS_LPCR && ((value & mask) == mask)) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 24ba7cc..426a847 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -115,6 +115,10 @@ msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status regist imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 +# imx7_snvs.c +imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32 +imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32 + # mos6522.c mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRIx64 " delta_next=0x%"PRIx64 |