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author | Blue Swirl <blauwirbel@gmail.com> | 2010-03-21 19:47:11 +0000 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2010-03-21 19:47:11 +0000 |
commit | 2d48377a8531de63ec1d0c4b9b1959dc4b78356c (patch) | |
tree | 5d953e12d529ea65102e1600dbcb14127261ea28 /hw | |
parent | d3ffc7a6e7372e1b88a4bf1c588cbe8ed46b2ca4 (diff) | |
download | qemu-2d48377a8531de63ec1d0c4b9b1959dc4b78356c.zip qemu-2d48377a8531de63ec1d0c4b9b1959dc4b78356c.tar.gz qemu-2d48377a8531de63ec1d0c4b9b1959dc4b78356c.tar.bz2 |
Compile serial only once
Push TARGET_WORDS_BIGENDIAN dependency to board level.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/mips_jazz.c | 18 | ||||
-rw-r--r-- | hw/mips_malta.c | 6 | ||||
-rw-r--r-- | hw/musicpal.c | 14 | ||||
-rw-r--r-- | hw/omap1.c | 22 | ||||
-rw-r--r-- | hw/pc.h | 3 | ||||
-rw-r--r-- | hw/ppc405_uc.c | 8 | ||||
-rw-r--r-- | hw/ppc440.c | 4 | ||||
-rw-r--r-- | hw/ppce500_mpc8544ds.c | 14 | ||||
-rw-r--r-- | hw/pxa2xx.c | 21 | ||||
-rw-r--r-- | hw/serial.c | 92 | ||||
-rw-r--r-- | hw/sm501.c | 15 | ||||
-rw-r--r-- | hw/sun4u.c | 2 |
12 files changed, 163 insertions, 56 deletions
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index ea74ea4..e8a81b1 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -254,10 +254,20 @@ void mips_jazz_init (ram_addr_t ram_size, i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); /* Serial ports */ - if (serial_hds[0]) - serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1); - if (serial_hds[1]) - serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1); + if (serial_hds[0]) { +#ifdef TARGET_WORDS_BIGENDIAN + serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); +#else + serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0); +#endif + } + if (serial_hds[1]) { +#ifdef TARGET_WORDS_BIGENDIAN + serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); +#else + serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0); +#endif + } /* Parallel port */ if (parallel_hds[0]) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 91498c2..96e3bc0 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -441,7 +441,11 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init); - s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1); +#ifdef TARGET_WORDS_BIGENDIAN + s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1); +#else + s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 0); +#endif malta_fpga_reset(s); qemu_register_reset(malta_fpga_reset, s); diff --git a/hw/musicpal.c b/hw/musicpal.c index b8af15e..7fc9fb3 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -1525,12 +1525,22 @@ static void musicpal_init(ram_addr_t ram_size, pic[MP_TIMER4_IRQ], NULL); if (serial_hds[0]) { +#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, - serial_hds[0], 1); + serial_hds[0], 1, 1); +#else + serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, + serial_hds[0], 1, 0); +#endif } if (serial_hds[1]) { +#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, - serial_hds[1], 1); + serial_hds[1], 1, 1); +#else + serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, + serial_hds[1], 1, 0); +#endif } /* Register flash */ @@ -1986,9 +1986,15 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base, s->base = base; s->fclk = fclk; s->irq = irq; +#ifdef TARGET_WORDS_BIGENDIAN s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, - chr ?: qemu_chr_open("null", "null", NULL), 1); - + chr ?: qemu_chr_open("null", "null", NULL), 1, + 1); +#else + s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, + chr ?: qemu_chr_open("null", "null", NULL), 1, + 0); +#endif return s; } @@ -2101,9 +2107,17 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) { /* TODO: Should reuse or destroy current s->serial */ +#ifdef TARGET_WORDS_BIGENDIAN s->serial = serial_mm_init(s->base, 2, s->irq, - omap_clk_getrate(s->fclk) / 16, - chr ?: qemu_chr_open("null", "null", NULL), 1); + omap_clk_getrate(s->fclk) / 16, + chr ?: qemu_chr_open("null", "null", NULL), 1, + 1); +#else + s->serial = serial_mm_init(s->base, 2, s->irq, + omap_clk_getrate(s->fclk) / 16, + chr ?: qemu_chr_open("null", "null", NULL), 1, + 0); +#endif } /* MPU Clock/Reset/Power Mode Control */ @@ -12,7 +12,8 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase, CharDriverState *chr); SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, qemu_irq irq, int baudbase, - CharDriverState *chr, int ioregister); + CharDriverState *chr, int ioregister, + int be); SerialState *serial_isa_init(int index, CharDriverState *chr); void serial_set_frequency(SerialState *s, uint32_t frequency); diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index bfcb791..df698a8 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -2182,11 +2182,11 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], /* Serial ports */ if (serial_hds[0] != NULL) { serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, - serial_hds[0], 1); + serial_hds[0], 1, 1); } if (serial_hds[1] != NULL) { serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, - serial_hds[1], 1); + serial_hds[1], 1, 1); } /* IIC controller */ ppc405_i2c_init(0xef600500, pic[2]); @@ -2535,11 +2535,11 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], /* Serial ports */ if (serial_hds[0] != NULL) { serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, - serial_hds[0], 1); + serial_hds[0], 1, 1); } if (serial_hds[1] != NULL) { serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, - serial_hds[1], 1); + serial_hds[1], 1, 1); } /* OCM */ ppc405_ocm_init(env); diff --git a/hw/ppc440.c b/hw/ppc440.c index 2ee7aea..d12cf71 100644 --- a/hw/ppc440.c +++ b/hw/ppc440.c @@ -89,11 +89,11 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, if (serial_hds[0] != NULL) { serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, - serial_hds[0], 1); + serial_hds[0], 1, 1); } if (serial_hds[1] != NULL) { serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, - serial_hds[1], 1); + serial_hds[1], 1, 1); } return env; diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 491ea7a..0901fa6 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -198,15 +198,17 @@ static void mpc8544ds_init(ram_addr_t ram_size, mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); /* Serial */ - if (serial_hds[0]) + if (serial_hds[0]) { serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE, - 0, mpic[12+26], 399193, - serial_hds[0], 1); + 0, mpic[12+26], 399193, + serial_hds[0], 1, 1); + } - if (serial_hds[1]) + if (serial_hds[1]) { serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE, - 0, mpic[12+26], 399193, - serial_hds[0], 1); + 0, mpic[12+26], 399193, + serial_hds[0], 1, 1); + } /* PCI */ pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4); diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index f8292e7..705c369 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -2076,9 +2076,15 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) for (i = 0; pxa270_serial[i].io_base; i ++) if (serial_hds[i]) +#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(pxa270_serial[i].io_base, 2, s->pic[pxa270_serial[i].irqn], 14857000/16, - serial_hds[i], 1); + serial_hds[i], 1, 1); +#else + serial_mm_init(pxa270_serial[i].io_base, 2, + s->pic[pxa270_serial[i].irqn], 14857000/16, + serial_hds[i], 1, 1); +#endif else break; if (serial_hds[i]) @@ -2187,12 +2193,19 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) s->pic[PXA2XX_PIC_MMC], s->dma); for (i = 0; pxa255_serial[i].io_base; i ++) - if (serial_hds[i]) + if (serial_hds[i]) { +#ifdef TARGET_WORDS_BIGENDIAN serial_mm_init(pxa255_serial[i].io_base, 2, s->pic[pxa255_serial[i].irqn], 14745600/16, - serial_hds[i], 1); - else + serial_hds[i], 1, 1); +#else + serial_mm_init(pxa255_serial[i].io_base, 2, + s->pic[pxa255_serial[i].irqn], 14745600/16, + serial_hds[i], 1, 0); +#endif + } else { break; + } if (serial_hds[i]) s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP], s->dma, serial_hds[i]); diff --git a/hw/serial.c b/hw/serial.c index f3ec36a..90213c4 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -825,65 +825,106 @@ static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, serial_ioport_write(s, addr >> s->it_shift, value & 0xFF); } -static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr) +static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; uint32_t val; val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF; -#ifdef TARGET_WORDS_BIGENDIAN val = bswap16(val); -#endif return val; } -static void serial_mm_writew(void *opaque, target_phys_addr_t addr, - uint32_t value) +static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; -#ifdef TARGET_WORDS_BIGENDIAN + uint32_t val; + + val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF; + return val; +} + +static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + SerialState *s = opaque; + value = bswap16(value); -#endif serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF); } -static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr) +static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + SerialState *s = opaque; + + serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF); +} + +static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; uint32_t val; val = serial_ioport_read(s, addr >> s->it_shift); -#ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); -#endif return val; } -static void serial_mm_writel(void *opaque, target_phys_addr_t addr, - uint32_t value) +static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr) +{ + SerialState *s = opaque; + uint32_t val; + + val = serial_ioport_read(s, addr >> s->it_shift); + return val; +} + +static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr, + uint32_t value) { SerialState *s = opaque; -#ifdef TARGET_WORDS_BIGENDIAN + value = bswap32(value); -#endif serial_ioport_write(s, addr >> s->it_shift, value); } -static CPUReadMemoryFunc * const serial_mm_read[] = { +static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + SerialState *s = opaque; + + serial_ioport_write(s, addr >> s->it_shift, value); +} + +static CPUReadMemoryFunc * const serial_mm_read_be[] = { &serial_mm_readb, - &serial_mm_readw, - &serial_mm_readl, + &serial_mm_readw_be, + &serial_mm_readl_be, }; -static CPUWriteMemoryFunc * const serial_mm_write[] = { +static CPUWriteMemoryFunc * const serial_mm_write_be[] = { &serial_mm_writeb, - &serial_mm_writew, - &serial_mm_writel, + &serial_mm_writew_be, + &serial_mm_writel_be, +}; + +static CPUReadMemoryFunc * const serial_mm_read_le[] = { + &serial_mm_readb, + &serial_mm_readw_le, + &serial_mm_readl_le, +}; + +static CPUWriteMemoryFunc * const serial_mm_write_le[] = { + &serial_mm_writeb, + &serial_mm_writew_le, + &serial_mm_writel_le, }; SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, qemu_irq irq, int baudbase, - CharDriverState *chr, int ioregister) + CharDriverState *chr, int ioregister, + int be) { SerialState *s; int s_io_memory; @@ -899,8 +940,13 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift, vmstate_register(base, &vmstate_serial, s); if (ioregister) { - s_io_memory = cpu_register_io_memory(serial_mm_read, - serial_mm_write, s); + if (be) { + s_io_memory = cpu_register_io_memory(serial_mm_read_be, + serial_mm_write_be, s); + } else { + s_io_memory = cpu_register_io_memory(serial_mm_read_le, + serial_mm_write_le, s); + } cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); } serial_update_msl(s); @@ -1226,10 +1226,17 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq, 2, -1, irq); /* bridge to serial emulation module */ - if (chr) - serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2, - NULL, /* TODO : chain irq to IRL */ - 115200, chr, 1); + if (chr) { +#ifdef TARGET_WORDS_BIGENDIAN + serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2, + NULL, /* TODO : chain irq to IRL */ + 115200, chr, 1, 1); +#else + serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2, + NULL, /* TODO : chain irq to IRL */ + 115200, chr, 1, 0); +#endif + } /* create qemu graphic console */ s->ds = graphic_console_init(sm501_update_display, NULL, @@ -771,7 +771,7 @@ static void sun4uv_init(ram_addr_t RAM_size, i = 0; if (hwdef->console_serial_base) { serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, - serial_hds[i], 1); + serial_hds[i], 1, 1); i++; } for(; i < MAX_SERIAL_PORTS; i++) { |